ST62E32BF1 STMicroelectronics, ST62E32BF1 Datasheet - Page 54

• Manufacturer Part Number: ST62E32BF1
• Description: 8-bit Microcontrollers - MCU UV EPROM 8K SPI/UART
• Manufacturer: STMicroelectronics

Specifications of ST62E32BF1

• Product Category: 8-bit Microcontrollers - MCU
• Core: ST6
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 8 MHz
• Program Memory Size: 7948 B
• Data Ram Size: 192 B
• On-chip Adc: Yes
• Package / Case: SDIP-42
• Mounting Style: Through Hole
• A/d Bit Size: 8 bit
• A/d Channels Available: 21
• Data Rom Size: 128 B
• Interface Type: SPI, UART
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Number Of Programmable I/os: 30
• Number Of Timers: 1 x 8 bit
• Program Memory Type: EPROM
• Factory Pack Quantity: 13
• Supply Voltage - Max: 5 V
• Supply Voltage - Min: 4.5 V

ST62T32B ST62E32B
CONTROL REGISTERS (Cont’d)
Status Control Register 3 (SCR3)
Address: E2h - Read/Write/Clear only
Bit 7 = CP2POL. CP2 Edge Polarity Select .
CP2POL defines the polarity for triggering the CP2
event.
A 0 defines the action on a falling edge on the CP2
input, a 1 on a rising edge.
Bit 6 = CP2IEN. CP2 Interrupt Enable . The Cap-
ture 2 Interrupt is masked when this bit is 0. Set-
ting the bit to 1 enables the CP2 event flag
CP2FLG to set the ARTIMER interrupt.
Bit 5 = CP2FLG. CP2 Interrupt Flag . When this bit
is 0, no CP2 event has occurred since the last
clear of this flag. If the bit is at 1, the first CP2
event and capture into CP has occurred.
This bit cannot be set by program, only cleared.
Bit 4 = CMPIEN. Compare Int. Enable . The Com-
pare Interrupt is masked when this bit is 0.
Setting the bit to 1 enables the Compare flag
CMPFLG to set the ARTIMER interrupt.
Bit 3 = CMPFLG. Compare Flag . When this bit is
0, no Masked-Compare True event has occurred
since the last clear of this flag. If the bit is at 1, a
54/83
CP2PO
7
L
CP2IE
N
CP2FL
G
CMPI-
EN
CMFLG
ZEROI-
EN
ROFLG
ZE-
PWM-
MD
0
Masked-Compare event has occurred.
This bit cannot be set by program, only cleared.
Bit 2 = ZEROIEN. Compare to Zero Int Enable.
The Masked-Counter Zero Interrupt is masked
when this bit is 0. Setting the bit to 1 enables the
ZEROFLG flag to set the ARTIMER interrupt.
Bit 1 = ZEROFLG. Compare to Zero Flag . When
this bit is 0, no Masked-Counter Zero event has
occurred since the last clear of this flag. If the bit is
at 1, a Masked-Counter Zero event has occurred
as the Masked Counter state equals 0 when run-
ning or on hold (not on Reset).
Bit 0 = PWMMD. PWM Output Mode Control . The
PWM Output mode is set by this bit; when 0, the
PWM output is run in set/reset mode (the PWM
output is set on a Masked-Counter Zero event and
is reset when on a Masked-Compare event).
When 1 the PWM output is in toggle mode; PWM
toggles its state on every Masked-Compare event.
Notes:
A Masked-Compare is the logical AND of the Mask
Register MASK with the Counter Register CT,
compared with the logical AND of the compare
Register CMP: [(MASK & CT) = (MASK&CMP)].
A Masked-Counter Zero is the logical AND of the
Mask Register MASK with the Counter Register
CT, compared with zero: [(MASK & CT) = 0000h]