ST62E32BF1 STMicroelectronics, ST62E32BF1 Datasheet - Page 47

• Manufacturer Part Number: ST62E32BF1
• Description: 8-bit Microcontrollers - MCU UV EPROM 8K SPI/UART
• Manufacturer: STMicroelectronics

Specifications of ST62E32BF1

• Product Category: 8-bit Microcontrollers - MCU
• Core: ST6
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 8 MHz
• Program Memory Size: 7948 B
• Data Ram Size: 192 B
• On-chip Adc: Yes
• Package / Case: SDIP-42
• Mounting Style: Through Hole
• A/d Bit Size: 8 bit
• A/d Channels Available: 21
• Data Rom Size: 128 B
• Interface Type: SPI, UART
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Number Of Programmable I/os: 30
• Number Of Timers: 1 x 8 bit
• Program Memory Type: EPROM
• Factory Pack Quantity: 13
• Supply Voltage - Max: 5 V
• Supply Voltage - Min: 4.5 V

The maximum time for downcounting is therefore
2
and Tclk the period of the main oscillator.
This down counter is stopped and its content kept
cleared as long as RUNRES bit is cleared.
4.3.1.1 Reload functions
The 16-bit down counter can be reloaded 3 differ-
ent ways:
At a zero overflow occurrence with the bit RELOAD
cleared: The counter is reloaded to FFFFh.
At a zero overflow occurrence with the bit
RELOAD set: The counter is reloaded with the val-
ue programmed in the RLCP register. For each
overflow, the transition between 0000h and the re-
load value (RLCP or FFFFh) is flagged through the
OVFFLG bit.
At an external event on pin CP1 or CP2 with the bit
RELOAD set: The counter is reloaded with the val-
ue programmed in the RLCP register.
As a consequence, the time between a timer re-
load and a zero overflow occurrence depends on
the value in RLCP when RELOAD bit is set. This
time is equal to (RLCP+1) x Psc x Tclk when
RELOAD bit is set, while it is 2
RELOAD bit is cleared.
4.3.1.2 Compare functions
The value in the counter CT is continuously com-
pared to 0000h and to the value programmed into
Figure 28. Flags Setting in Compare and Reload Functions
16
x Psc x Tclk where Psc is the prescaler ratio,
COMPFLG
ZEROFLG
OVFFLG
Value CT
Counter
16
x Psc x Tclk when
CMP
the Compare Register CMP. The comparison
range to 0000h and CMP is defined by using the
MASK register to select which bits are used, there-
fore the comparisons performed are:
– MASK&CT = ? MASK&CMP.
– MASK&CT = ? 0000h.
When a matched comparison to 0000h or
MASK&CMP occurs, the flags ZEROFLG and
COMPFLG are respectively set.
By using MASK values reported in
MASK register works as counter frequency multi-
plier for the compare functions. In that case posi-
tive masked comparison occur with a period of
2
most significant bit of MASK value.
Table 17. Recommended Mask Values
Note: Writing 0000h in MASK gives a period equal
to two times the prescaled period Psc x Tclk.
Hexadecimal
(n+1)
Software Reset
FFFFh
7FFFh
3FFFh
1FFFh
0FFFh
0007h
0003h
0001h
...
x Psc x Tclk where n is the position of the
0
1111 1111 1111 1111
0111 1111 1111 1111
0011 1111 1111 1111
0001 1111 1111 1111
0000 1111 1111 1111
0000 0000 0000 0111
0000 0000 0000 0011
0000 0000 0000 0001
Software Reset
FFFFh
RLCP
or
Binary
ST62T32B ST62E32B
Software Reset
...
Table
position,n
MSbit at 1
17, the
15
14
13
12
11
2
1
0
47/83