ST62E32BF1 STMicroelectronics, ST62E32BF1 Datasheet - Page 51

• Manufacturer Part Number: ST62E32BF1
• Description: 8-bit Microcontrollers - MCU UV EPROM 8K SPI/UART
• Manufacturer: STMicroelectronics

Specifications of ST62E32BF1

• Product Category: 8-bit Microcontrollers - MCU
• Core: ST6
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 8 MHz
• Program Memory Size: 7948 B
• Data Ram Size: 192 B
• On-chip Adc: Yes
• Package / Case: SDIP-42
• Mounting Style: Through Hole
• A/d Bit Size: 8 bit
• A/d Channels Available: 21
• Data Rom Size: 128 B
• Interface Type: SPI, UART
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Number Of Programmable I/os: 30
• Number Of Timers: 1 x 8 bit
• Program Memory Type: EPROM
• Factory Pack Quantity: 13
• Supply Voltage - Max: 5 V
• Supply Voltage - Min: 4.5 V

TIMINGS MEASUREMENT MODES (Cont’d)
CP2 triggered restart mode with CP2 event de-
tection.
This mode is enabled for RLDSEL2=1 and
RLDSEL1=0.
As long as RUNRES bit is set, an external event
on CP2 pin generates both, at first the capture into
CP, and then the reload from RLCP. Capture into
CP on CP2 event is enabled only if CP2FLG and
CP2ERR are cleared, otherwise only reload func-
tions from RLCP are performed.
An external event on CP1 activates CP1FLG or
CP1ERR flags without any impact on the reload or
capture functions.
Figure 31. CP2 Triggered Restart Mode with CP2 Event Detection
Figure 32. Software Triggered Restart Mode with CP2 Event Detection
COUNTER
RUNRES
CP2
CP2
CP1
CP1
CT
Then Reload CT from RLCP
First Capture CT into CP
CP2 disabled
Set CP2FLG
Load Counter from RLCP and Startup
CP1 disabled
0000h
Set CP1FLG
Set CP1FLG
Set CP1ERR
Reload CT from RLCP
Capture CT into CP
Set CP2ERR
Set CP2FLG
Note: After Reset, the first CP2 event will capture
the 0000h state of the counter into CP and then
will restart the counter after loading it from RLCP.
CP2FLG flag must always be cleared to execute
another capture into CP.
Software triggered restart mode with CP2
event detection.
This mode is enabled for RLDSEL2=0 and
RLDSEL1=0.
RUNRES bit setting initiates the reload and startup
of the downcounting, while CP2 is used as strobe
source for the CT capture into CP register.
Set CP1ERR
Reload CT from RLCP
ST62T32B ST62E32B
Set CP2ERR
Software Reset
No action
CP1 disabled
VR02007C
VR02007D
0000h
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