VRS51C1100-40-Q Cypress Semiconductor, VRS51C1100-40-Q Datasheet - Page 12

• Manufacturer Part Number: VRS51C1100-40-Q
• Description: 8-bit Microcontrollers - MCU 128K+1K 40MHz 5V
• Manufacturer: Cypress Semiconductor

Specifications of VRS51C1100-40-Q

• Product Category: 8-bit Microcontrollers - MCU
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 40 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 1 KB
• Operating Supply Voltage: 4.5 V to 5.5 V
• Package / Case: QFP-44
• Mounting Style: SMD/SMT
• Data Rom Size: 128 B
• Interface Type: UART
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Program Memory Type: Flash
• Factory Pack Quantity: 96
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 4.5 V

MOVX @DPTR instruction, but is limited as a read
function. The MPAGE register default setting is 00h.
T
Data Bank Control Register
The DBANK register enables the data bank select
function to map the entire contents of the RAM
memory in the range of 40h to 7Fh for applications that
require direct addressing of the expanded RAM
contents.
The data bank select function is activated by setting
the data bank select enable bit (BSE) to 1. Setting this
bit to zero disables the function. The lower nibble of
this register controls the mapping of the entire 1KB
bytes on-chip RAM space into the 040h-07Fh range.
T
______________________________________________________________________________________________
www.ramtron.com
ABLE
ABLE
BSE
Bit
7
6
5
4
3
2
1
0
VRS51C1100
7
7
13: MPAGE
14: D
Mnemonic
BSE
Unused
Unused
Unused
BS3
BS2
BS1
BS0
ATA
6
6
B
ANK
REGISTER
Unused
C
ONTROL
5
5
(MPAGE) - SFR 85
Description
Data Bank Select Enable Bit
BSE=1, Data Bank Select enabled
BSE=0, Data Bank Select disabled
-
-
-
Allows the mapping of the 1KB RAM into
the 040h - 07Fh RAM space
R
EGISTER
4
MPAGE[7:0]
4
(DBANK) – SFR 86
3
BS3
3
H
2
BS2
2
H
1
BS1
1
BS0
0
0
Windowed access to the entire 1KB of on-chip RAM in
the range of 40h-7Fh is described in the following
table.
T
Example: User writes #55h to address 203h:
ABLE
BS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
15: B
ANK MAPPING DIRECT ADDRESSING MODE
BS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
MOV
MOV
MOV
BS1
DBANK, #8CH
A, #55H
43H, A
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
BSO
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
00C0h-00FFh
01C0h-01FFh
02C0h-02FFh
0080h-00BFh
0280h-02BFh
0000h-003Fh
0040h-007Fh
0100h-013Fh
0140h-017Fh
0180h-01BFh
0200h-023Fh
0240h-027Fh
0C0h-0FFh
040h~07fh
000h-03Fh
040h-07Fh
080h-0BFh
mapping
address
;Set bank mapping 40h-07Fh to
0200h-023Fh
;Store #55H to A
;Write #55H to 0203h ;address
On-chip expanded
On-chip expanded
On-chip expanded
On-chip expanded
On-chip expanded
On-chip expanded
On-chip expanded
On-chip expanded
On-chip expanded
On-chip expanded
On-chip expanded
page 12 of 50
On-chip expanded
Lower 128 bytes
Lower 128 bytes
Upper 128 bytes
Upper 128 bytes
768 bytes RAM
768 bytes RAM
768 bytes RAM
768 bytes RAM
768 bytes RAM
768 bytes RAM
768 bytes RAM
768 bytes RAM
768 bytes RAM
768 bytes RAM
768 bytes RAM
768 bytesRAM
Note
RAM
RAM
RAM
RAM