ZLF645E0H2864G00TR Maxim Integrated, ZLF645E0H2864G00TR Datasheet - Page 147

• Manufacturer Part Number: ZLF645E0H2864G00TR
• Description: 8-bit Microcontrollers - MCU Crimzon Flash Infrared MCU
• Manufacturer: Maxim Integrated

Specifications of ZLF645E0H2864G00TR

• Core: Z8
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 8 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 1 KB
• Operating Supply Voltage: 2 V to 3.6 V
• Package / Case: SSOP-28
• Mounting Style: SMD/SMT
• Interface Type: UART
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Number Of Programmable I/os: 5
• Number Of Timers: 2 x 8 bit, 1 x 16 bit
• Processor Series: ZLF645
• Program Memory Type: Flash

19-4572; Rev 0; 4/09
Voltage Brownout Standby
STOP Mode
HALT Mode
An on-chip voltage comparator circuit (VBO) checks that the V
for correct operation of the device in terms of Flash memory reads. A second on-chip
comparator circuit (subVBO) checks that the V
tion of the VBO circuit. If the V
be held in a reset state as long as V
and XTAL2 oscillator circuitry will be disabled thereby stopping the clock input to the
ZLF645 and saving power. If the V
point, the ZLF645 will remain in a reset state and the VBO comparator circuit will be 
disabled for further power savings. When the power level returns to a value above the
VBO trip point, the device performs a power-on reset and functions normally.
STOP
ing the MCU supply current to a very low level. For STOP mode current specifications,
see
To enter STOP mode, first flush the instruction pipeline to avoid suspending execution in
mid-instruction. Execute a NOP instruction (OpCode =
appropriate sleep instruction, as given below:
STOP mode is terminated only by a reset, such as WDT time-out, POR, or one of the Stop
Mode Recovery events as described in
This condition causes the processor to restart the application program at address
Unlike a normal POR or WDT reset, a Stop Mode Recovery reset does not reset the
contents of some registers and bits. Register bits not reset by a Stop Mode Recovery are
highlighted in grey in the register tables. Register bit SMR[7] is set to 1 by a Stop Mode
Recovery.
HALT
The counter/timers, UART, and interrupts (IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, and IRQ5)
remain active. The devices are recovered by interrupts, either externally or internally 
generated. An interrupt request must be executed (enabled) to exit HALT mode. After the
interrupt service routine, the program continues from the instruction after HALT mode.
Table 80
FF
6F
instruction turns OFF the internal clock and external crystal oscillation, thus reduc-
instruction turns off the internal CPU clock, but not the XTAL oscillation.
on page 165.
NOP
STOP
DD
DD
level drops below the VBO trip point, the ZLF645 will
; clear the pipeline
; enter STOP mode
DD
remains below this trip point value, and the XTAL1
Stop Mode Recovery Event Sources
level continues to drop below the subVBO trip
DD
level is high enough for proper opera-
ZLF645 Series Flash MCUs
FFh
) immediately before the
DD
Product Specification
Voltage Brownout Standby
is at the required level
on page 144.
000Ch
.
139