AT89C51RC2-RLTIL Atmel, AT89C51RC2-RLTIL Datasheet - Page 80

• Manufacturer Part Number: AT89C51RC2-RLTIL
• Description: 8-bit Microcontrollers - MCU 80C31 w/4k
• Manufacturer: Atmel

Specifications of AT89C51RC2-RLTIL

• Product Category: 8-bit Microcontrollers - MCU
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 60 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 1280 B
• On-chip Adc: No
• Operating Supply Voltage: 2.7 V to 5.5 V
• Package / Case: VQFP-44
• Mounting Style: SMD/SMT
• Interface Type: SPI, UART
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Program Memory Type: Flash
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V

Power Management
Reset
Cold Reset
80
AT89C51RB2/RC2
Two power reduction modes are implemented in the AT89C51RB2/RC2: the Idle mode
and the Power-down mode. These modes are detailed in the following sections. In addi-
tion to these power reduction modes, the clocks of the core and peripherals can be
dynamically divided by 2 using the X2 mode detailed in Section “X2 Feature”.
In order to start-up (cold reset) or to restart (warm reset) properly the microcontroller, an
high level has to be applied on the RST pin. A bad level leads to a wrong initialization of
the internal registers like SFRs, Program Counter… and to unpredictable behavior of
the microcontroller. A proper device reset initializes the AT89C51RB2/RC2 and vectors
the CPU to address 0000h. RST input has a pull-down resistor allowing power-on reset
by simply connecting an external capacitor to V
can be applied either directly on the RST pin or indirectly by an internal reset source
such as the watchdog timer. Resistor value and input characteristics are discussed in
the Section “DC Characteristics” of the AT89C51RB2/RC2 datasheet.
Figure 32. Reset Circuitry and Power-On Reset
2 conditions are required before enabling a CPU start-up:
•
•
If one of these 2 conditions are not met, the microcontroller does not start correctly and
can execute an instruction fetch from anywhere in the program space. An active level
applied on the RST pin must be maintained till both of the above conditions are met. A
reset is active when the level V
period of time where V
taken into account to determine the reset pulse width:
•
•
To determine the capacitor value to implement, the highest value of these 2 parameters
has to be chosen. Table 1 gives some capacitor values examples for a minimum R
50 KΩ and different oscillator startup and V
V
The level on X1 input pin must be outside the specification (V
V
Oscillator startup time.
RST
DD
DD
must reach the specified V
rise time,
RST input circuitry
VDD
VSS
P
DD
and the oscillator are not stabilized. 2 parameters have to be
IH1
DD
is reached and when the pulse width covers the
range
DD
rise times.
From Internal
Reset Source
To CPU Core
and Peripherals
DD
as shown in Figure 32. A warm reset
IH
Power-on Reset
, V
VDD
IL
)
+
4180E–8051–10/06
RST
RST
of