AT89C51RC2-SLRUL Atmel, AT89C51RC2-SLRUL Datasheet
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AT89C51RC2-SLRUL
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AT89C51RC2-SLRUL Summary of contents
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... The Flash memory can be programmed either in parallel mode or in serial mode with the ISP capability or with software. The programming voltage is internally generated from the standard VCC pin. Power Supply CC 8-bit Microcontroller with 16K/ 32K Bytes Flash AT89C51RB2 AT89C51RC2 Rev. 4180E–8051–10/06 ...
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... The added features of the AT89C51RB2/RC2 make it more powerful for applications that need pulse width modulation, high speed I/O and counting capabilities such as alarms, motor control, corded phones, and smart card readers. Table 1. Memory Size Part Number Flash (Bytes) AT89C51RB2 16K AT89C51RC2 32K AT89C51IC2 32K TOTAL RAM XRAM (Bytes) (Bytes) 1024 ...
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Block Diagram Figure 1. Block Diagram XTAL1 XTAL2 ALE/ PROG PSEN EA (2) RD (2) WR Notes: 1. Alternate function of Port 1. 2. Alternate function of Port 3. 4180E–8051–10/06 (2) (2) EUART Flash RAM XRAM + 32Kx8 or 256x8 ...
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SFR Mapping AT89C51RB2/RC2 4 The Special Function Registers (SFRs) of the AT89C51RB2/RC2 fall into the following categories: • C51 core registers: ACC, B, DPH, DPL, PSW, SP • I/O port registers: P0, P1, P2, P3 • Timer registers: T2CON, T2MOD, ...
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Table 2. C51 Core SFRs Mnemonic Add Name ACC E0h Accumulator B F0h B Register PSW D0h Program Status Word SP 81h Stack Pointer DPL 82h Data Pointer Low Byte DPH 83h Data Pointer High Byte Table 3. System Management ...
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Table 6. Timer SFRs Mnemonic Add Name TCON 88h Timer/Counter 0 and 1 Control TMOD 89h Timer/Counter 0 and 1 Modes TL0 8Ah Timer/Counter 0 Low Byte TH0 8Ch Timer/Counter 0 High Byte TL1 8Bh Timer/Counter 1 Low Byte TH1 ...
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Table 8. Serial I/O Port SFRs Mnemonic Add Name SCON 98h Serial Control SBUF 99h Serial Data Buffer SADEN B9h Slave Address Mask SADDR A9h Slave Address BDRCON 9Bh Baud Rate Control BRL 9Ah Baud Rate Reload Table 9. SPI ...
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Table 11 shows all SFRs with their address and their reset value. Table 11. SFR Mapping Bit addressable 0/8 1/9 CH F8h 0000 0000 B F0h 0000 0000 CL E8h 0000 0000 ACC E0h 0000 0000 CCON CMOD D8h 00X0 ...
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Pin Configurations Figure 2. Pin Configurations P1.0/ P1.1/T2EX/ P1.2/ECI 3 37 P1.3CEX0 4 P1.4/CEX1 P1.5/CEX2/MISO 6 34 P1.6/CEX3/SCK P1.7CEX4/MOSI RST 9 32 P3.0/RxD 10 31 PDIL40 P3.1/TxD 30 11 ...
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Table 12. Pin Description for Pin Packages Pin Number Mnemonic DIL LCC VQFP44 1 P0 P1 ...
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Table 12. Pin Description for Pin Packages (Continued) Pin Number Mnemonic DIL LCC VQFP44 1.4 P1.0 - P1.7 XTAL1 19 21 XTAL2 18 20 P2 P3.0 - P3.7 10 ...
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Table 12. Pin Description for Pin Packages (Continued) Pin Number Mnemonic DIL LCC VQFP44 1.4 PSEN AT89C51RB2/RC2 12 Type Name and Function 26 O Program Strobe Enable: The read strobe to external ...
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Port Types Figure 3. Quasi-Bidirectional Output Port Latch Data 4180E–8051–10/06 AT89C51RB2/RC2 I/O ports (P1, P2, P3) implement the quasi-bidirectional output that is common on the 80C51 and most of its derivatives. This output type can be used as both an ...
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Oscillator Registers AT89C51RB2/RC2 14 To optimize the power consumption and execution time needed for a specific task, an internal, prescaler feature has been implemented between the oscillator and the CPU and peripherals. Table 13. CKRL Register CKRL – Clock Reload ...
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Functional Block Diagram Figure 4. Functional Oscillator Block Diagram Reset F Xtal1 OSC Osc Xtal2 :2 Prescaler Divider 4180E–8051–10/06 Reload CKRL 1 8-bit 0 Prescaler-Divider X2 CKCON0 • A hardware RESET puts the prescaler divider in the following state: • ...
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Enhanced Features X2 Feature Description AT89C51RB2/RC2 16 In comparison to the original 80C52, the AT89C51RB2/RC2 implements some new fea- tures, which are : • X2 option • Dual Data Pointer • Extended RAM • Programmable Counter Array (PCA) • Hardware ...
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Figure 6. Mode Switching Waveforms XTAL1 XTAL1:2 X2 Bit CPU Clock x1 Mode 4180E–8051–10/06 F OSC X2 Mode The X2 bit in the CKCON0 register (see Table 15) allows a switch from 12 clock periods per instruction to 6 clock ...
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AT89C51RB2/RC2 18 Table 15. CKCON0 Register CKCON0 - Clock Control Register (8Fh WDX2 PCAX2 Bit Bit Number Mnemonic Description 7 Reserved Watchdog Clock (This control bit is validated when the CPU clock X2 is set; when ...
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Table 16. CKCON1 Register CKCON1 - Clock Control Register (AFh Bit Bit Number Mnemonic Description 7 - Reserved 6 - Reserved 5 - Reserved 4 - Reserved 3 - Reserved 2 - Reserved ...
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Dual Data Pointer Register (DPTR) Figure 7. Use of Dual Pointer 7 AUXR1(A2H) AT89C51RB2/RC2 20 The additional data pointer can be used to speed up code execution and reduce code size. The dual DPTR structure is a way by which ...
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Table 17. AUXR1 register AUXR1- Auxiliary Register 1(0A2h ENBOOT Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - The ...
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AT89C51RB2/RC2 22 INC is a short (2 Bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. However, note that the INC instruction does not directly force the DPS bit to a particular state, but ...
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Expanded RAM (XRAM) Figure 8. Internal and External Data Memory Address 0FFh or 3FFh XRAM 00 4180E–8051–10/06 The AT89C51RB2/RC2 provides additional bytes of random access memory (RAM) space for increased data parameter handling and high-level language usage. AT89C51RB2/RC2 devices have ...
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AT89C51RB2/RC2 24 • Instructions that use indirect addressing access the Upper 128 Bytes of data RAM. For example: MOV @R0, # data where R0 contains 0A0h, accesses the data Byte at address 0A0h, rather than P2 (whose address is 0A0h). ...
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Registers 4180E–8051–10/06 Table 19. AUXR Register AUXR - Auxiliary Register (8Eh DPU - M0 Bit Bit Number Mnemonic Description Disable Weak Pull-up 7 DPU Cleared to activate the permanent weak pull up when latch data is logical ...
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... The auto-reload mode configures Timer 16-bit timer or event counter with auto- matic reload. If DCEN bit in T2MOD is cleared, Timer 2 behaves as in 80C52 (see the Atmel C51 Microcontroller Hardware description). If DCEN bit is set, Timer 2 acts as an Up/down timer/counter as shown in Figure 9. In this mode the T2EX pin controls the direction of count ...
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Programmable Clock-out Mode 4180E–8051–10/06 Figure 9. Auto-Reload Mode Up/Down Counter (DCEN = CLK PERIPH 6 In the clock-out mode, Timer 2 operates as a 50% duty-cycle, programmable clock gen- erator (see Figure 10). The input clock increments ...
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AT89C51RB2/RC2 28 Figure 10. Clock-Out Mode C/ FCLK PERIPH T2 T2EX TR2 T2CON TL2 2 TH (8-bit) (8-bit) RCAP2L RCAP2H (8-bit) (8-bit) Toggle Q D T2OE T2MOD EXF2 T2CON EXEN2 T2CON OVER- FLOW TIMER 2 INTERRUPT 4180E–8051–10/06 ...
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Registers 4180E–8051–10/06 Table 20. T2CON Register T2CON – Timer 2 Control Register (C8h TF2 EXF2 RCLK Bit Bit Number Mnemonic Description Timer 2 Overflow Flag 7 TF2 Must be cleared by software. Set by hardware on Timer ...
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AT89C51RB2/RC2 30 Table 21. T2MOD Register T2MOD – Timer 2 Mode Control Register (C9h Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this ...
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Programmable Counter Array (PCA) 4180E–8051–10/06 The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accu- racy. The PCA consists of a dedicated timer/counter which serves as the ...
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Figure 11. PCA Timer/Counter F /6 CLK PERIPH F /2 CLK PERIPH T0 OVF P1.2 Idle AT89C51RB2/RC2 32 CH CIDL WDTE CPS1 CPS0 CF CR CCF4 CCF3 CCF2 CCF1 CCF0 To PCA Modules overflow CL 16-bit up Counter CMOD ECF ...
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Registers 4180E–8051–10/06 Table 22. CMOD Register CMOD – PCA Counter Mode Register (D9h CIDL WDTE - Bit Bit Number Mnemonic Description Counter Idle Control 7 CIDL Cleared to program the PCA Counter to continue functioning during idle ...
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AT89C51RB2/RC2 34 Table 23. CCON Register CCON – PCA Counter Control Register (D8h Bit Bit Number Mnemonic Description PCA Counter Overflow Flag Set by hardware when the counter rolls over. CF flags an interrupt ...
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Figure 12. PCA Interrupt System PCA Timer/Counter Module 0 Module 1 Module 2 Module 3 Module 4 CMOD. 0 4180E–8051–10/ CCF4 CCF3 CCF2 CCF1 CCF0 ECCFn CCAPMn. 0 ECF PCA Modules: each one of the five compare/capture Modules ...
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AT89C51RB2/RC2 36 Table 24. CCAPMn Registers (n = 0-4) CCAPM0 – PCA Module 0 Compare/Capture Control Register (0DAh) CCAPM1 – PCA Module 1 Compare/Capture Control Register (0DBh) CCAPM2 – PCA Module 2 Compare/Capture Control Register (0DCh) CCAPM3 – PCA Module ...
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Table 25. PCA Module Modes (CCAPMn Registers) ECOMn CAPPn CAPNn MATn ...
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AT89C51RB2/RC2 38 Table 27. CCAPnL Registers (n = 0-4) CCAP0L – PCA Module 0 Compare/Capture Control Register Low (0EAh) CCAP1L – PCA Module 1 Compare/Capture Control Register Low (0EBh) CCAP2L – PCA Module 2 Compare/Capture Control Register Low (0ECh) CCAP3L ...
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PCA Capture Mode Figure 13. PCA Capture Mode CF Cex. n ECOMn 4180E–8051–10/06 To use one of the PCA Modules in the capture mode either one or both of the CCAPM bits CAPN and CAPP for that Module must be ...
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Software Timer/ Compare Mode Figure 14. PCA Compare Mode and PCA Watchdog Timer Write to CCAPnL Reset Write to CCAPnH Enable 1 0 AT89C51RB2/RC2 40 The PCA Modules can be used as software timers by setting both the ECOM ...
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High-speed Output Mode Figure 15. PCA High-speed Output Mode Write to CCAPnL Write to CCAPnH 0 1 4180E–8051–10/06 In this mode the CEX output (on port 1) associated with the PCA module will toggle each time a match occurs between ...
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Pulse Width Modulator Mode PCA Watchdog Timer AT89C51RB2/RC2 42 All of the PCA Modules can be used as PWM outputs. Figure 16 shows the PWM func- tion. The frequency of the output depends on the source for the PCA timer. ...
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Modules would not be a good idea. Thus, in most appli- cations the first solution is the best option. This watchdog timer won’t generate a reset out on the reset pin. AT89C51RB2/RC2 43 ...
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Serial I/O Port Framing Error Detection AT89C51RB2/RC2 44 The serial I/O port in the AT89C51RB2/RC2 is compatible with the serial I/O port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as a Universal Asynchronous Receiver ...
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Automatic Address Recognition Given Address 4180E–8051–10/06 Figure 19. UART Timings in Modes 2 and 3 RXD D0 D1 Start bit RI SMOD0=0 RI SMOD0=1 FE SMOD0=1 The automatic address recognition feature is enabled when the multiprocessor commu- nication feature is ...
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Broadcast Address Reset Addresses AT89C51RB2/RC2 46 The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB don’t-care bit; for slaves B and C, bit 1.To ...
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Registers Baud Rate Selection for UART for Mode 1 and 3 4180E–8051–10/06 Table 30. SADEN Register SADEN - Slave Address Mask Register (B9h Reset Value = 0000 0000b Not bit addressable Table 31. SADDR Register SADDR - ...
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Internal Baud Rate Generator (BRG) Figure 21. Internal Baud Rate AT89C51RB2/RC2 48 Table 32. Baud Rate Selection Table UART TCLK RCLK (T2CON) (T2CON) (BDRCON ...
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Table 33. SCON Register SCON - Serial Control Register (98h FE/SM0 SM1 SM2 Bit Bit Number Mnemonic Description Framing Error bit (SMOD0=1) Clear to reset the error state, not cleared by a valid stop bit. FE ...
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UART Registers AT89C51RB2/RC2 50 Table 34. Example of Computed Value When X2=1, SMOD1=1, SPD=1 Baud Rates F = 16. 384 MHz OSC BRL 115200 247 57600 238 38400 229 28800 220 19200 203 9600 149 4800 43 Table 35. Example ...
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Table 38. SBUF Register SBUF - Serial Buffer Register for UART (99h Reset Value = XXXX XXXXb Table 39. BRL Register BRL - Baud Rate Reload Register for the internal baud rate generator, UART (9Ah) 7 ...
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AT89C51RB2/RC2 52 Table 40. T2CON Register T2CON - Timer 2 Control Register (C8h TF2 EXF2 RCLK Bit Bit Number Mnemonic Timer 2 overflow Flag 7 TF2 Must be cleared by software. Set by hardware on timer 2 ...
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Table 41. PCON Register PCON - Power Control Register (87h SMOD1 SMOD0 - Bit Bit Number Mnemonic Serial port Mode bit 1 for UART 7 SMOD1 Set to select double baud rate in mode 1, 2 ...
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AT89C51RB2/RC2 54 Table 42. BDRCON Register BDRCON - Baud Rate Control Register (9Bh Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit ...
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Interrupt System Figure 22. Interrupt Control System INT0 TF0 INT1 TF1 PCA TF2 EXF2 KBD IT SPI IT Individual Enable 4180E–8051–10/06 The AT89C51RB2/RC2 has a total of 9 interrupt vectors: two external interrupts (INT0 and INT1), three ...
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Registers AT89C51RB2/RC2 56 A low-priority interrupt can be interrupted by a high-priority interrupt, but not by another low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt source. Table 43. Priority Level Bit Values IPH ...
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Table 44. IENO Register IEN0 - Interrupt Enable Register (A8h ET2 Bit Bit Number Mnemonic Description Enable All Interrupt Bit 7 EA Cleared to disable all interrupts. Set to enable all interrupts. PCA Interrupt ...
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AT89C51RB2/RC2 58 Table 45. IPL0 Register IPL0 - Interrupt Priority Register (B8h PPCL PT2L Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. PCA ...
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Table 46. IPH0 Register IPH0 - Interrupt Priority High Register (B7h PPCH PT2H Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. PCA ...
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AT89C51RB2/RC2 60 Table 47. IEN1 Register IEN1 - Interrupt Enable Register (B1h Bit Bit Number Mnemonic Description 7 - Reserved 6 - Reserved 5 - Reserved 4 - Reserved 3 - Reserved SPI Interrupt ...
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Table 48. IPL1 Register IPL1 - Interrupt Priority Register (B2h Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 ...
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AT89C51RB2/RC2 62 Table 49. IPH1 Register IPH1 - Interrupt Priority High Register (B3h Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. ...
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Interrupt Sources and Vector Addresses 4180E–8051–10/06 Table 50. Interrupt Sources and Vector Addresses Number Polling Priority Interrupt Source Keyboard 9 9 AT89C51RB2/RC2 ...
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Keyboard Interface Interrupt Power Reduction Mode AT89C51RB2/RC2 64 The AT89C51RB2/RC2 implements a keyboard interface allowing the connection matrix keyboard based on 8 inputs with programmable interrupt capability on both high or low level. ...
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Registers 4180E–8051–10/06 Table 51. KBF Register KBF - Keyboard Flag Register (9Eh KBF7 KBF6 KBF5 Bit Bit Number Mnemonic Description Keyboard Line 7 Flag Set by hardware when the Port line 7 detects a programmed level. It ...
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AT89C51RB2/RC2 66 Table 52. KBE Register KBE - Keyboard Input Enable Register (9Dh KBE7 KBE6 KBE5 Bit Bit Number Mnemonic Description Keyboard Line 7 Enable Bit 7 KBE7 Cleared to enable standard I/O pin. Set to enable ...
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Table 53. KBLS Register KBLS - Keyboard Level Selector Register (9Ch KBLS7 KBLS6 KBLS5 Bit Bit Number Mnemonic Description Keyboard Line 7 Level Selection Bit 7 KBLS7 Cleared to enable a low level detection on Port ...
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Serial Port Interface (SPI) Features Signal Description Master Output Slave Input (MOSI) Master Input Slave Output (MISO) SPI Serial Clock (SCK) Slave Select (SS) AT89C51RB2/RC2 68 The Serial Peripheral Interface Module (SPI) allows full-duplex, synchronous, serial communication between the MCU ...
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Baud Rate 4180E–8051–10/06 drive the network. The Master may select each Slave device by software through port pins (Figure 26). To prevent bus conflicts on the MISO line, only one slave should be selected at a time by the Master ...
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Functional Description Operating Modes AT89C51RB2/RC2 70 Figure 26 shows a detailed structure of the SPI Module. Figure 26. SPI Module Block Diagram FCLK PERIPH /4 Clock /8 /16 Divider /32 /64 /128 Clock Select SPR2 SPEN SSDIS SPI Interrupt Request ...
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Master Mode Slave Mode Transmission Formats 4180E–8051–10/06 Figure 27. Full-Duplex Master-Slave Interconnection MISO 8-bit Shift register MOSI SPI SCK Clock Generator SS VDD Master MCU The SPI operates in Master mode when the Master bit, MSTR is set. Only one ...
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Figure 28. Data Transmission Format (CPHA = 0) SCK Cycle Number SPEN (Internal) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (from Master) MISO (from Slave) SS (to Slave) Capture Point Figure 29. Data Transmission Format (CPHA = 1) ...
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Error Conditions Mode Fault (MODF) Write Collision (WCOL) Overrun Condition SS Error Flag (SSERR) Interrupts 4180E–8051–10/06 The following flags in the SPSTA signal SPI error conditions: Mode Fault error in Master mode SPI indicates that the level on the Slave ...
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Registers Serial Peripheral Control Register (SPCON) AT89C51RB2/RC2 74 Figure 31. SPI Interrupt Requests Generation SPIF SPI Transmitter CPU Interrupt Request MODF SPI Receiver/error CPU Interrupt Request SSDIS There are three registers in the Module that provide control, status and data ...
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Serial Peripheral Status Register (SPSTA) 4180E–8051–10/06 Bit Number Bit Mnemonic Description SPR2 SPR1 SPR0 1 1 Reset Value = 0001 0100b Not bit addressable The Serial Peripheral Status Register contains flags to ...
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Serial Peripheral DATa Register (SPDAT) AT89C51RB2/RC2 76 Bit Bit Number Mnemonic Description Reserved 1 - The value read from this bit is indeterminate. Do not set this bit. Reserved 0 - The value read from this bit is indeterminate. Do ...
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Hardware Watchdog Timer Using the WDT 4180E–8051–10/06 The WDT is intended as a recovery method in situations where the CPU may be sub- jected to software upset. The WDT consists of a 14-bit counter and the Watchdog Timer Reset (WDTRST) ...
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WDT During Power-down and Idle AT89C51RB2/RC2 78 Table 60. WDTPRG Register WDTPRG - Watchdog Timer Out Register (0A7h Bit Bit Number Mnemonic Description Reserved 5 - The value read from ...
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ONCE Mode (ON Chip Emulation) 4180E–8051–10/06 The ONCE mode facilitates testing and debugging of systems using AT89C51RB2/RC2 without removing the circuit from the board. The ONCE mode is invoked by driving cer- tain pins of the AT89C51RB2/RC2; the following ...
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Power Management Reset Cold Reset AT89C51RB2/RC2 80 Two power reduction modes are implemented in the AT89C51RB2/RC2: the Idle mode and the Power-down mode. These modes are detailed in the following sections. In addi- tion to these power reduction modes, the ...
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Warm Reset Watchdog Reset 4180E–8051–10/06 Table 1. Minimum Reset Capacitor Value for a 50 kΩ Pull-down Resistor Oscillator Start-Up Time 820 2.7 µF Note: These values assume V DD on/off sequences is too ...
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Reset Recommendation to Prevent Flash Corruption Idle Mode Power-down Mode AT89C51RB2/RC2 82 An example of bad initialization situation may occur in an instance where the bit ENBOOT in AUXR1 register is initialized from the hardware bit BLJB upon reset. Since ...
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Figure 34. Power-down Exit Waveform INT0 INT1 XTALA or XTALB Active Phase Table 62. State of Ports Mode Program Memory Idle Internal Idle External Power Down Internal Power Down External 4180E–8051–10/06 be the one following the instruction that puts the ...
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Power-off Flag AT89C51RB2/RC2 84 The Power-off flag allows the user to distinguish between a “cold start” reset and a “warm start” reset. A cold start reset is the one induced still applied to the device and ...
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Reduced EMI Mode 4180E–8051–10/06 The ALE signal is used to demultiplex address and data buses on port 0 when used with external program or data memory. Nevertheless, during internal code execution, ALE signal is still generated. In order to reduce ...
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Flash EEPROM Memory Features Flash Programming and Erasure AT89C51RB2/RC2 86 The Flash memory increases EPROM and ROM functionality with in-circuit electrical erasure and programming. It contains 16K or 32K Bytes of program memory organized in 128 or 256 pages of ...
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Flash Registers and Memory Map Hardware Register Flash Memory Lock Bits 4180E–8051–10/06 The AT89C51RB2/RC2 Flash memory uses several registers for its management: • Hardware registers can only be accessed through the parallel programming modes which are handled by the parallel ...
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... Several registers are used, in factory and by parallel programmers, to make copies of hardware registers contents. These values are used by Atmel ISP. These registers are in the "Extra Flash Memory" part of the Flash memory. This block is also called "XAF" or eXtra Array Flash. They are accessed in the following ways: • ...
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... The two lock bits provide different levels of protection for the on-chip code and data, when programmed as shown in Table 69. AT89C51RB2/RC2 Default value Description FCh 101x 1011b 0FFh FFh 58h ATMEL D7h C51 X2, Electrically Erasable F7h AT89C51RB2/RC2 32KB FBh AT89C51RB2/RC2 16 KB AT89C51RB2/RC2 32KB, EFh Revision 0 ...
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Flash Memory Status Figure 35. Flash Memory Possible Contents 7FFFh T89C51RC2 32KB 3FFFh T89C51RB2 16KB Virgin 0000h Default Memory Organization AT89C51RB2/RC2 90 Table 69. Program Lock Bits of the SSB Program Lock Bits Security level LB0 LB1 Protection Description 1 ...
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Bootloader Architecture Introduction Acronyms 4180E–8051–10/06 The bootloader manages a communication according to a specific defined protocol to provide the whole access and service on Flash memory. Furthermore, all accesses and routines can be called from the user application. Figure 36. ...
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Functional Description Figure 37. Bootloader Functional Description Exernal Host with Specific Protocol Communication AT89C51RB2/RC2 92 ISP Communication Management Flash Memory Management Flash Memory On the above diagram, the on-chip bootloader processes are: • ISP Communication Management The purpose of this ...
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Bootloader Functionality Introduction Figure 38. Hardware conditions typical sequence during power-on. 4180E–8051–10/06 The bootloader can be activated by two means: Hardware conditions or regular boot process. The Hardware conditions ( PSEN = 0) during the Reset# falling edge ...
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... ENBOOT bit (AUXR1) is cleared Yes (PSEN = and ALE = 1 or not connected) FCON = 00h Hardware Condition? FCON = F0h BLJB = 1 BLJB!= 0 ENBOOT = 0 ? BLJB = 0 ENBOOT = 1 F800h yes = hardware boot FCON = 00h ? BSB = 00h ? SBV = FCh ? USER BOOT LOADER PC= [SBV]00h conditions Atmel BOOT LOADER 4180E–8051–10/06 ...
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ISP Protocol Description Physical Layer Frame Description 4180E–8051–10/06 The UART used to transmit information has the following configuration: • Character: 8-bit data • Parity: none • Stop: 1 bit • Flow control: none • Baud rate: autobaud is performed by ...
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Functional Description Software Security Bits (SSB) AT89C51RB2/RC2 96 The SSB protects any Flash access from ISP command. The command "Program Software Security bit" can only write a higher priority level. There are three levels of security: • level 0: NO_SECURITY ...
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... When the communication is initialized the protocol depends on the record type requested by the host. FLIP, a software utility to implement ISP programming with a PC, is available from the Atmel the web site. The host initializes the communication by sending a ’U’ character to help the bootloader to compute the baudrate (autobaud). ...
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Autobaud Performances Table 72. Autobaud Performances Frequency (MHz) Baudrate (bit/s) 1.8432 2400 OK 4800 OK 9600 OK 19200 OK 38400 57600 115200 Frequency (MHz) Baudrate (bit/s) 10 2400 OK 4800 OK 9600 OK 19200 OK 38400 57600 115200 Command Data ...
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... This flow is common to the following frames: • Flash/EEPROM Programming Data Frame • EOF or Atmel Frame (only Programming Atmel Frame) • Config Byte Programming Data Frame • Baud Rate Frame Write Command ’X’ & CR & LF ’ ...
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... Example AT89C51RB2/RC2 100 Programming Data (write 55h at address 0010h in the Flash) HOST : 01 0010 BOOTLOADER : 01 0010 Programming Atmel function (write SSB to level 2) HOST : 02 0000 BOOTLOADER : 02 0000 F5 Writing Frame (write BSB to 55h) HOST : 03 0000 BOOTLOADER : 03 0000 4180E–8051–10/06 ...
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Blank Check Command Description Figure 43. Blank Check Flow Host Send Blank Check Command OR Wait Checksum Error COMMAND ABORTED Wait COMMAND_OK OR COMMAND FINISHED Wait Address not erased COMMAND FINISHED Example 4180E–8051–10/06 Blank Check Command ’X’ & CR & ...
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Display Data Description Figure 44. Display Flow Host Send Display Command OR Wait Checksum Error COMMAND ABORTED OR Wait Security Error COMMAND ABORTED Wait Display Data All data read COMMAND FINISHED Note: The maximum size of block is 400h. To ...
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... CR LF This flow is similar for the following frames: • Reading Frame • EOF Frame/Atmel Frame (only reading Atmel Frame) Read Command ’X’ & CR & LF ’L’ & CR & LF ’value’ & ’.’ & CR & LF Read function (read SBV) ...
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ISP Commands Summary AT89C51RB2/RC2 104 Table 73. ISP Commands Summary Command Command Name Data[0] 00h Program Data 03h Write Function Data[0:1] = start address Data [2:3] = end address 04h Display Function Data[4] = 00h -> Display data Data[4] = ...
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... API “PROGRAM DATA PAGE” call. Indeed, this API call writes up to 128 Bytes in a sin- gle command. All routines for software access are provided in the C Flash driver available at Atmel’s web site. The API calls description and arguments are shown in Table 74. ...
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Table 74. API Call Summary (Continued) Command R1 A Fuse value PROGRAM X2 FUSE 0Ah 00h or 01h Fuse value PROGRAM BLJB 0Ah FUSE 00h or 01h READ HSB 0Bh XXh READ BOOT ID1 0Eh XXh READ BOOT ID2 0Eh ...
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Characteristics E Absolute Maximum Ratings C = commercial......................................................0°C to 70° industrial ........................................................-40°C to 85°C Storage Temperature .................................... -65° 150°C Voltage (standard voltage) .........-0. 6. Voltage on V ...
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T = -40°C to +85° 0V =2.7V to 5.5V and MHz (both internal and external code execution =4.5V to 5.5V and MHz (internal ...
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DC Parameters for Low Voltage T = 0°C to +70° 0V -40°C to +85° 0V Symbol Parameter V Input Low Voltage IL V Input High Voltage ...
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If I exceeds the test condition than the listed test conditions. 7. For other values, please contact your sales office. 8. Icc Flash Write operation current while an on-chip flash page write is on going. AT89C51RB2/RC2 110 may ...
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AC Parameters Explanation of the AC Symbols External Program Memory Characteristics 4180E–8051–10/06 Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The other characters, depending on their positions, stand for the name of ...
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AT89C51RB2/RC2 112 Table 76. AC Parameters for a Fix Clock Symbol -M Min LHLL T 5 AVLL T 5 LLAX T LLIV T 5 LLPL T 50 PLPH T PLIV T 0 PXIX T PXIZ T ...
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External Program Memory Read Cycle ALE PSEN PORT 0 INSTR IN ADDRESS PORT 2 OR SFR-P2 External Data Memory Characteristics 4180E–8051–10/ LHLL LLIV T LLPL T PLPH T LLAX T PLIV T T AVLL TPLAZ PXIX ...
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AT89C51RB2/RC2 114 Table 79. AC Parameters for a Fix Clock -M Symbol Min T 125 RLRH T 125 WLWH T RLDV T 0 RHDX T RHDZ T LLDV T AVDV T 45 LLWL T 70 AVWL T 5 QVWX T ...
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External Data Memory Write Cycle ALE PSEN WR PORT 0 ADDRESS PORT 2 OR SFR-P2 4180E–8051–10/06 Standard Symbol Type Clock X2 Clock T Min RLRH T Min ...
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External Data Memory Read Cycle ALE PSEN RD PORT 0 ADDRESS PORT 2 OR SFR-P2 Serial Port Timing - Shift Register Mode AT89C51RB2/RC2 116 T LLDV T LLWL T AVDV T LLAX A0-A7 T RLAZ T AVWL ADDRESS A8-A15 OR ...
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Shift Register Timing Waveforms 0 INSTRUCTION ALE CLOCK T QVXH OUTPUT DATA WRITE to SBUF INPUT DATA CLEAR RI External Clock Drive Waveforms AC Testing Input/Output Waveforms Float Waveforms Clock Waveforms 4180E–8051–10/ XLXL T XHQX ...
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Figure 50. Internal Clock Signals STATE4 INTERNAL CLOCK P1 P2 XTAL2 ALE EXTERNAL PROGRAM MEMORY FETCH PSEN P0 DATA SAMPLED FLOAT P2 (EXT) READ CYCLE WRITE CYCLE PORT OPERATION MOV PORT SRC MOV DEST ...
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... AT89C51RB2-RLTCM 16 KBytes AT89C51RB2-RLTIM AT89C51RB2-SLSIL AT89C51RB2-RLTIL AT89C51RC2-3CSCM AT89C51RC2-3CSIM AT89C51RC2-SLSCM AT89C51RC2-SLSIM 32 KBytes AT89C51RC2-RLTCM AT89C51RC2-RLTIM AT89C51RC2-SLSIL AT89C51RC2-RLTIL AT89C51RB2-3CSUM AT89C51RB2-SLSUM AT89C51RB2-RLTUM 16 KBytes AT89C51RB2-SLSUL AT89C51RB2-RLTUL AT89C51RB2-RLTUM AT89C51RC2-3CSUM AT89C51RC2-SLSUM AT89C51RC2-RLTUM 32 KBytes AT89C51RC2-SLSUL AT89C51RC2-RLTUL 4180E–8051–10/06 Supply Voltage Temperature Range 5V Industrial 5V Commercial 5V Industrial 5V Commercial 5V Industrial 3V Industrial 3V Industrial ...
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Package Information PDIL40 AT89C51RB2/RC2 120 4180E–8051–10/06 ...
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VQFP44 4180E–8051–10/06 AT89C51RB2/RC2 121 ...
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PLC44 AT89C51RB2/RC2 122 4180E–8051–10/06 ...
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Datasheet Change Log Changes from 4180A- 08/02 to 4180B-04/03 Changes from 4180B- 04/03 to 4180C-12/03 Changes from 4180C- 12/03 - 4180D - 06/05 Changes from 4180D - 06/05 to 4180E - 10/06 4180E–8051–10/06 1. Changed the endurance of Flash to ...
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Table of Contents Features ................................................................................................. 1 Description ............................................................................................ 1 Block Diagram ....................................................................................... 3 SFR Mapping ......................................................................................... 4 Pin Configurations ................................................................................ 9 Port Types ........................................................................................... 13 Oscillator ............................................................................................. 14 Enhanced Features ............................................................................. 16 Dual Data Pointer Register (DPTR) ................................................... 20 Expanded ...
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Registers............................................................................................................. 47 Baud Rate Selection for UART for Mode 1 and 3............................................... 47 UART Registers.................................................................................................. 50 Interrupt System ................................................................................. 55 Registers............................................................................................................. 56 Interrupt Sources and Vector Addresses............................................................ 63 Keyboard Interface ............................................................................. 64 Registers............................................................................................................. 65 Serial Port Interface (SPI) ................................................................... ...
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DC Parameters for Standard Voltage ............................................................... 107 DC Parameters for Low Voltage ....................................................................... 109 AC Parameters ................................................................................................. 111 Ordering Information ........................................................................ 119 Package Information ........................................................................ 120 PDIL40.............................................................................................................. 120 VQFP44 ............................................................................................................ 121 PLC44............................................................................................................... 122 Datasheet Change Log ..................................................................... 123 Changes ...
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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...