AT89C51RC2-RLTIL Atmel, AT89C51RC2-RLTIL Datasheet - Page 74

• Manufacturer Part Number: AT89C51RC2-RLTIL
• Description: 8-bit Microcontrollers - MCU 80C31 w/4k
• Manufacturer: Atmel

Specifications of AT89C51RC2-RLTIL

• Product Category: 8-bit Microcontrollers - MCU
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 60 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 1280 B
• On-chip Adc: No
• Operating Supply Voltage: 2.7 V to 5.5 V
• Package / Case: VQFP-44
• Mounting Style: SMD/SMT
• Interface Type: SPI, UART
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Program Memory Type: Flash
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V

Registers
Serial Peripheral Control
Register (SPCON)
74
AT89C51RB2/RC2
Figure 31. SPI Interrupt Requests Generation
There are three registers in the Module that provide control, status and data storage functions. These registers
are describes in the following paragraphs.
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•
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Table 56 describes this register and explains the use of each bit
Table 56. SPCON Register
SPCON - Serial Peripheral Control Register (0C3H)
Bit Number
SPR2
SPIF
MODF
SSDIS
The Serial Peripheral Control Register does the following:
Selects one of the Master clock rates
Configure the SPI Module as Master or Slave
Selects serial clock polarity and phase
Enables the SPI Module
Frees the SS pin for a general-purpose
7
7
6
5
4
3
2
SPEN
6
Bit Mnemonic
SSDIS
MSTR
SPR2
SPEN
CPOL
CPHA
SPI Transmitter
CPU Interrupt Request
SSDIS
SPI Receiver/error
CPU Interrupt Request
5
Description
Serial Peripheral Rate 2
Bit with SPR1 and SPR0 define the clock rate.
Serial Peripheral Enable
Cleared to disable the SPI interface.
Set to enable the SPI interface.
SS Disable
Cleared to enable SS in both Master and Slave modes.
Set to disable SS in both Master and Slave modes. In Slave mode,
this bit has no effect if CPHA =’0’. When SSDIS is set, no MODF
interrupt request is generated
Serial Peripheral Master
Cleared to configure the SPI as a Slave.
Set to configure the SPI as a Master.
Clock Polarity
Cleared to have the SCK set to ’0’ in idle state.
Set to have the SCK set to ’1’ in idle low.
Clock Phase
Cleared to have the data sampled when the SCK leaves the idle
state (see CPOL).
Set to have the data sampled when the SCK returns to idle state (see
CPOL).
MSTR
4
CPOL
3
CPU Interrupt Request
SPI
.
CPHA
2
SPR1
1
4180E–8051–10/06
SPR0
0