C8051F537-ITR Silicon Labs, C8051F537-ITR Datasheet - Page 20
![no-image](/images/no-image-200.jpg)
C8051F537-ITR
Manufacturer Part Number
C8051F537-ITR
Description
8-bit Microcontrollers - MCU 2KB 12ADC 125C 20Pin MCU
Manufacturer
Silicon Labs
Datasheet
1.C8051F536-ITR.pdf
(220 pages)
Specifications of C8051F537-ITR
Product Category
8-bit Microcontrollers - MCU
Rohs
yes
Core
8051
Data Bus Width
8 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
2 KB
Data Ram Size
256 B
On-chip Adc
Yes
Package / Case
TSSOP-20
Mounting Style
SMD/SMT
A/d Bit Size
12 bit
A/d Channels Available
16
Interface Type
SPI, UART
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
16
Number Of Timers
3
On-chip Dac
No
Processor Series
C8051
Program Memory Type
Flash
Factory Pack Quantity
2500
Supply Voltage - Max
2.7 V, 5.25 V
Supply Voltage - Min
2 V, 2.7 V
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C8051F52x/F53x
1.3. On-Chip Memory
The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data
RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general
purpose RAM, and direct addressing accesses the 128 byte SFR address space. The lower 128 bytes of
RAM are accessible via direct and indirect addressing. The first 32 bytes are addressable as four banks of
general purpose registers, and the next 16 bytes can be byte addressable or bit addressable.
Program memory consists of 7680 bytes (’F520/0A/1/1A and ’F530/0A/1/1A), 4 kB (’F523/3A/4/4A and
C8051F53x/53xA), or 2 kB (’F526/6A/7/7A and ’F536/6A/7/7A) of Flash. This memory is byte writable and
erased in 512-byte sectors, and requires no special off-chip programming voltage.
20
0x1DFF
0x0FFF
0x1E00
0x07FF
0x0000
0x1000
0x0000
0x0800
0x0000
PROGRAM/DATA MEMORY
'F520/0A/1/1A and 'F530/0A/1/1A
'F523/3A/4/4A and 'F533/3A/4/4A
'F526/6A/7/7A and 'F536/6A/7/7A
Programmable in 512
Programmable in 512
Programmable in 512
Byte Sectors)
Byte Sectors)
Byte Sectors)
RESERVED
RESERVED
RESERVED
(In-System
(In-System
(In-System
8 kB Flash
4 kB Flash
2 kB Flash
(Flash)
Figure 1.6. Memory Map
0xFF
0x7F
0x2F
0x20
0x1F
0x80
0x30
0x00
Rev. 1.4
(Indirect Addressing
(Direct and Indirect
INTERNAL DATA ADDRESS SPACE
General Purpose
Upper 128 RAM
Bit Addressable
Addressing)
Registers
Only)
DATA MEMORY (RAM)
(Direct Addressing Only)
Special Function
Lower 128 RAM
(Direct and Indirect
Addressing)
Register's
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