C8051F537-ITR Silicon Labs, C8051F537-ITR Datasheet - Page 108

• Manufacturer Part Number: C8051F537-ITR
• Description: 8-bit Microcontrollers - MCU 2KB 12ADC 125C 20Pin MCU
• Manufacturer: Silicon Labs

Specifications of C8051F537-ITR

• Product Category: 8-bit Microcontrollers - MCU
• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 2 KB
• Data Ram Size: 256 B
• On-chip Adc: Yes
• Package / Case: TSSOP-20
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 16
• Interface Type: SPI, UART
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 16
• Number Of Timers: 3
• On-chip Dac: No
• Processor Series: C8051
• Program Memory Type: Flash
• Factory Pack Quantity: 2500
• Supply Voltage - Max: 2.7 V, 5.25 V
• Supply Voltage - Min: 2 V, 2.7 V

C8051F52x/F53x
11.2. Power-Fail Reset / V
C8051F52x-C/F53x-C devices include two V
level-sensitive V
allow safe erase or write of Flash memory from firmware. VDDMON1 is used to hold the device in a reset
state during power-up and brownout conditions.
Note: VDDMON1 is not present in older silicon revisions A and B. Please refer to Section “20.4. VDD Monitors and
When a power-down transition or power irregularity causes V
monitors (VDDMON0 and VDDMON1) will drive the RST pin low and hold the CIP-51 in a reset state (see
Figure 11.2). When V
Note that even though internal data memory contents are not altered by the power-fail reset, it is impossi-
ble to determine if V
data may no longer be valid.
VDDMON0 is enabled and is selected as a reset source after power-on resets; however its defined state
(enabled/disabled) is not altered by any other reset source. For example, if VDDMON0 is disabled by soft-
ware, and a software reset is performed, VDDMON0 will still be disabled after that reset.
VDDMON1 is enabled and is selected as a reset source after power-on reset and any other type of reset.
There is no register setting that can disable this level-sensitive VDD monitor as a reset source.
To protect the integrity of Flash contents, the V
higher setting (VDMLVL = '1') and selected as a reset source if software contains routines which
erase or write Flash memory. If the V
erase or write performed on Flash memory will cause a Flash Error device reset.
Note: Please refer to Section “20.5. VDD Monitor (VDDMON0) High Threshold Setting” on page 212 for important
The V
VDDMON0 as a reset source before it is enabled and stabilized may cause a system reset. The procedure
for re-enabling the V
1. Enable the V
2. Wait for the V
3. Select the V
See Figure 11.2 for V
See Table 2.8 on page 32 for complete electrical characteristics of the V
Note:
11.2.1. VDD Monitor Thresholds and Minimum VDD
The minimum operating digital supply voltage (V
age at which the MCU is released from reset (V
thresholds that are specified in Table 2.8 on page 32. This could allow code execution during the power-up
108
This delay should be omitted if software contains routines which write or erase Flash memory.
DD
VDD Ramp Time” on page 211 for more details. 
notes related to the VDD Monitor high threshold setting in older silicon revisions A and B. 
Software should take care not to inadvertently disable the V
source when writing to RSTSRC to enable other reset sources or to trigger a software reset. All
writes to RSTSRC should explicitly set PORSF to '1' to keep the V
source.
monitor (VDDMON0) must be enabled before it is selected as a reset source. Selecting the

DD
DD
DD
DD
monitor as a reset source (PORSF bit in RSTSRC = 1).
monitor (VDMEN bit in VDDMON = 1).
monitor (VDDMON1). VDDMON0 is primarily intended for setting a higher threshold to
monitor to stabilize (see Table 2.8 on page 32 for the V
DD
DD
DD
DD
dropped below the level required for data retention. If the PORSF flag reads 1, the
monitor and configuring the V
monitor timing; note that the reset delay is not incurred after a V
returns to a level above V
DD
Monitors (VDDMON0 and VDDMON1)
DD
monitor is not enabled and set to the higher setting, any
DD
DD
RST
Rev. 1.4
monitors: a standard V
) is specified as 2.0 V in Table 2.2 on page 26. The volt-
RST
) can be as low as 1.65 V based on the V
DD
DD
, the CIP-51 will be released from the reset state.
monitor as a reset source is shown below:
monitor (VDDMON0) must be enabled to the
DD
DD
to drop below V
Monitor (VDDMON0) as a reset
DD
DD
DD
DD
monitor.
Monitor enabled as a reset
monitor (VDDMON0) and a
Monitor turn-on time). Note:
RST
, the power supply
DD
monitor reset.
DD
Monitor