IDT70V27L35PFI IDT, Integrated Device Technology Inc, IDT70V27L35PFI Datasheet
IDT70V27L35PFI
Specifications of IDT70V27L35PFI
800-1392
Available stocks
Related parts for IDT70V27L35PFI
IDT70V27L35PFI Summary of contents
Page 1
... Features: True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed access – Commercial: 15/20/25/35/55ns (max.) – Industrial: 20/35ns (max.) Low-power operation – IDT70V27S Active: 500mW (typ.) Standby: 3.3mW (typ.) – IDT70V27L Active: 500mW (typ.) Standby: 660 µ W (typ.) ...
Page 2
... This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking. Commercial and Industrial Temperature Range reads or writes to any location in memory. An automatic power down feature controlled by the chip enables ( circuitry of each port to enter a very low standby power mode. ...
Page 3
IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM Pin Configurations (1,2,3) 07/29/ 10L 14L ...
Page 4
IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM Truth Table I – Chip Enable < 0. >V -0. NOTES: 1. Chip Enable references are shown above ...
Page 5
IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM Absolute Maximum Ratings Symbol Rating (2) V Terminal Voltage TERM with Respect to GND T Temperature BIAS Under Bias T Storage STG Temperature I DC Output OUT Current NOTES: 1. ...
Page 6
IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter Dynamic Operating SEM = V Current (Both Ports Active) (3) f ...
Page 7
IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter Dynamic Operating Current I DD SEM = V (Both Ports Active ...
Page 8
IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol READ CYCLE t Read Cycle Time RC t Address Access Time AA (3) t Chip Enable Access Time ...
Page 9
IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM Waveform of Read Cycles ADDR ( UB, LB R/W DATA OUT BUSY OUT Timing of Power-Up Power-Down ( NOTES: 1. Timing depends on ...
Page 10
IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Symbol WRITE CYCLE t Write Cycle Time WC (3) t Chip Enable to End-of-Write EW t Address Valid to End-of-Write ...
Page 11
... access RAM and SEM = access semaphore 10. Refer to Chip Enable Truth Table ( ( ( ( LOW CE and a LOW R/W for memory array writing cycle. WP and SEM = Commercial and Industrial Temperature Range (1,5, allow the I/O drivers to turn off and data to be placed must be met for either condition. ...
Page 12
IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM Timing Waveform of Semaphore Read after Write Timing, Either Side VALID ADDRESS t AW SEM I R/W OE Write Cycle NOTES ...
Page 13
IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol BUSY TIMING (M/S BUSY Access Time from Address Match t BAA BUSY Disable Time from Address ...
Page 14
IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM Timing Waveform of Write with Port-to-Port Read and BUSY ADDR "A" R/W "A" DATA IN "A" (1) t APS ADDR "B" BUSY "B" DATA OUT "B" NOTES ensure ...
Page 15
IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM Waveform of BUSY Arbitration Controlled by CE Timing (M ADDR "A" and "B" CE "A" (2) t APS CE "B" BUSY "B" Waveform of BUSY Arbitration Cycle Controlled ...
Page 16
IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM Waveform of Interrupt Timing ADDR "A" ( "A" R/W "A" t INS INT "B" ADDR "B" ( "B" OE "B" t INR INT "B" ...
Page 17
... SRAM location. If the interrupt func-tion is not used, address locations 7FFE and 7FFF are not used as mail boxes, but as part of the random access memory. Refer to Truth Table IV for the interrupt operation. Busy Logic Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the RAM is “ ...
Page 18
IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM the other side is completed write operation has been attempted from the side that receives a BUSY indication, the write signal is gated internally to prevent the write ...
Page 19
... The eight semaphore flags reside within the IDT70V27 in a separate memory space from the Dual-Port RAM. This address space is accessed by placing a low input on the SEM pin (which acts as a chip select for the semaphore flags) and using the other control pins (Address, OE, and R/W) as they would be used in accessing a standard Static RAM ...
Page 20
IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM Ordering Information XXXXX A A 999 Device Power Speed Type NOTES: 1. Industrial temperature range is available on selected TQFP packages in low power. For other speeds, packages and powers ...
Page 21
IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM Datasheet Document History(cont'd) 01/12/01: Page 1 Page 6 Page 7 & 8 08/02/04: Page 1, 4 & 20 Page 2 & 3 Page Page 5 Page 6 ...