LHF00L15 Sharp Microelectronics, LHF00L15 Datasheet - Page 16

• Manufacturer Part Number: LHF00L15
• Description: IC FLASH 32MBIT 90NS 48TSOP
• Manufacturer: Sharp Microelectronics

Specifications of LHF00L15

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 32M (2M x 16)
• Speed: 90ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 425-1884

SR.7 = WRITE STATE MACHINE STATUS (WSMS)
SR.15 - SR.8 = RESERVED FOR FUTURE
SR.6 = BLOCK ERASE SUSPEND STATUS (BESS)
SR.5, SR.4 = ERASE, PROGRAM STATUS (EPS)
SR.3 = WP#/ACC STATUS (WPACCS)
SR.2 = PROGRAM SUSPEND
SR.1 = DEVICE PROTECT STATUS (DPS)
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
ENHANCEMENTS (R)
WSMS
1 = Ready
0 = Busy
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
SR.5=1 and SR.4=1: Command Sequence Error
SR.5=1 or SR.4=1: Error in Block Erase, Full Chip
SR.5=0 and SR.4=0: Successful Block Erase, Full Chip
1 = V
0 = WP#/ACC OK
1 = Program Suspended
0 = Program in Progress/Completed
1 = Erase or Program Attempted on a
0 = Unlocked
15
R
7
Erase, Program or OTP Program
Erase, Program or OTP Program
Operation Abort
Locked Block, Operation Abort
STATUS (PSS)
CC
+0.4V < WP#/ACC < 11.7V Detect,
BESS
14
R
6
EPS
13
R
5
Table 8. Status Register Definition
EPS
12
R
4
LHF00L15
Status Register indicates the status of the WSM (Write State
Machine).
Check SR.7 or RY/BY# to determine block erase, full chip
erase, program or OTP program completion. SR.6 - SR.1 are
invalid while SR.7="0".
If both SR.5 and SR.4 are "1"s after a block erase, full chip
erase, program, set/clear block lock bit, set block lock-down
bit attempt, an improper command sequence was entered.
For the period of time required to check the status register in
erase and program operation, refer to the specifications of
block erase, full chip erase, program and OTP Program time.
SR.3 does not provide a continuous indication of WP#/ACC
level. The WSM interrogates and indicates the WP#/ACC
level only after Block Erase, Full Chip Erase, Program or
OTP Program command sequences. SR.3 is not guaranteed to
report accurate feedback when WP#/ACC≠V
SR.1 does not provide a continuous indication of block lock
bit. The WSM interrogates the block lock bit only after Block
Erase, Full Chip Erase, Program or OTP Program command
sequences. It informs the system, depending on the attempted
operation, if the block lock bit is set. Reading the block lock
configuration codes after writing the Read Identifier Codes/
OTP command indicates block lock bit status.
SR.15 - SR.8 and SR.0 are reserved for future use and should
be masked out when polling the status register.
WPACCS
11
R
3
PSS
10
R
2
NOTES:
DPS
R
9
1
ACCH
Rev. 2.45
.
R
R
8
0
13