W9412G6JH-5 Winbond Electronics, W9412G6JH-5 Datasheet - Page 7

• Manufacturer Part Number: W9412G6JH-5
• Description: IC DDR-400 SDRAM 128MB 66TSSOPII
• Manufacturer: Winbond Electronics

Specifications of W9412G6JH-5

• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 66-TSOPII
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5. PIN DESCRIPTION
11, 13, 54, 56, 57,
59, 60, 62, 63, 65
6, 12, 52, 58, 64
2, 4, 5, 7, 8, 10,
PIN NUMBER
3, 9, 15, 55, 61
14, 17, 19, 25,
42, 43, 50, 53
23, 22, 21
34, 48, 66
1, 18, 33
28 − 32,
35 − 41
26, 27
20, 47
45, 46
16,51
24
44
49
LDM, UDM
CAS , WE
BA0, BA1
A0 − A11
NAME
LDQS,
DQ0 −
UDQS
DQ15
V
CLK,
V
V
RAS ,
CKE
CLK
PIN
V
V
NC
CS
DDQ
SSQ
REF
DD
SS
Reference Voltage V
Data Input/ Output
Command Inputs
Differential Clock
No Connection
Ground for I/O
Clock Enable
Power for I/O
FUNCTION
Bank Select
Data Strobe
Chip Select
Write Mask
Address
Ground
Power
Inputs
Buffer
Buffer
Multiplexed pins for row and column address.
Row address: A0 − A11.
Column address: A0 − A8. (A10 is used for Auto-precharge)
Select bank to activate during row address latch time, or
bank to read/write during column address latch time.
The DQ0 – DQ15 input and output data are synchronized
with both edges of DQS.
DQS is Bi-directional signal. DQS is input signal during write
operation and output signal during read operation. It is Edge-
aligned with read data, Center-aligned with write data.
Disable or enable the command decoder. When command
decoder is disabled, new command is ignored and previous
operation continues.
Command inputs (along with
being entered.
When DM is asserted “high” in burst write, the input data is
masked. DM is synchronized with both edges of DQS.
All address and control input signals are sampled on the
crossing of the positive edge of CLK and negative edge of
CKE controls the clock activation and deactivation. When
CKE is low, Power Down mode, Suspend mode, or Self
Refresh mode is entered.
Power for logic circuit inside DDR SDRAM.
Ground for logic circuit inside DDR SDRAM.
Separated power from V
improve noise.
Separated ground from V
improve noise.
No connection
CLK
REF
- 7 -
.
is reference voltage for inputs.
Publication Release Date: Apr. 02, 2010
DESCRIPTION
DD
SS
, used for output buffer, to
, used for output buffer, to
CS
) define the command
W9412G6JH
Revision A01