CY7C1383D-133AXI Cypress Semiconductor Corp, CY7C1383D-133AXI Datasheet - Page 9

• Manufacturer Part Number: CY7C1383D-133AXI
• Description: IC SRAM 18MBIT 133MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Synchronousr

Specifications of CY7C1383D-133AXI

• Memory Size: 18M (1M x 18)
• Package / Case: 100-LQFP
• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Access Time: 6.5 ns
• Maximum Clock Frequency: 133 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Current: 210 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Ports: 2
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2149; CY7C1383D-133AXI

Truth Table
Document #: 38-05544 Rev. *F
Notes:
Deselected Cycle, Power
Down
Deselected Cycle, Power
Down
Deselected Cycle, Power
Down
Deselected Cycle, Power
Down
Deselected Cycle, Power
Down
Sleep Mode, Power Down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
4. X=Don't Care, H = Logic HIGH, L = Logic LOW.
5. WRITE = L when any one or more byte write enable signals, and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.
6. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
7. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is
the ADSP or with the assertion of ADSC . As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't
care for the remainder of the write cycle.
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Cycle Description
[4, 5, 6, 7, 8]
ADDRESS
External
External
External
External
External
Current
Current
Current
Current
Current
Current
Used
None
None
None
None
None
None
Next
Next
Next
Next
Next
Next
CE
H
X
X
X
X
H
H
X
H
X
X
H
H
X
H
L
L
L
L
L
L
L
L
1
CE
X
X
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
L
2
CE
H
X
X
X
X
X
X
X
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
3
ZZ
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
ADSP
X
H
H
X
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L
L
L
L
ADSC
X
H
H
H
H
H
H
H
H
H
H
H
H
L
X
X
L
L
X
X
L
L
L
CY7C1381D, CY7C1381F
CY7C1383D, CY7C1383F
X
ADV WRITE
. Writes may occur only on subsequent clocks after
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
L
L
L
L
L
L
H
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
L
L
L
L
L
OE
X
X
X
X
X
X
H
X
H
H
H
X
X
H
H
X
X
L
L
L
L
L
L
CLK
L-H Tri-State
L-H Tri-State
L-H Tri-State
L-H Tri-State
L-H Tri-State
L-H Q
L-H Tri-State
L-H D
L-H Q
L-H Tri-State
L-H Q
L-H Tri-State
L-H Q
L-H Tri-State
L-H D
L-H D
L-H Q
L-H Tri-State
L-H Q
L-H Tri-State
L-H D
L-H D
X
Page 9 of 29
Tri-State
DQ
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