CY7C1383D-133AXI Cypress Semiconductor Corp, CY7C1383D-133AXI Datasheet
CY7C1383D-133AXI
Specifications of CY7C1383D-133AXI
CY7C1383D-133AXI
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CY7C1383D-133AXI Summary of contents
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... Separate processor and controller address strobes • Synchronous self-timed write • Asynchronous output enable • CY7C1381D/CY7C1383D available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball FBGA package. CY7C1381F/CY7C1383F available in Pb-free and non Pb-free 119-ball BGA package • ...
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... WRITE REGISTER DQ DQP , WRITE REGISTER DQ DQP BYTE BWE WRITE REGISTER GW ENABLE CE1 REGISTER CE2 CE3 OE SLEEP Logic Block Diagram – CY7C1383D/CY7C1383F ADDRESS A0,A1,A REGISTER MODE ADV DQ ,DQP ,DQP BWE GW ENABLE SLEEP CONTROL Note: 3. CY7C1381F and CY7C1383F have only 1 chip enable (CE Document #: 38-05544 Rev. *F ...
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... TQFP Pinout (3 Chip Enable) DQP DDQ V 5 SSQ SSQ V 11 DDQ /DNU CY7C1381D NC 16 (512K x 36 DDQ V 21 SSQ SSQ V 27 DDQ DQP 30 D Document #: 38-05544 Rev. *F CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F 80 DQP DDQ 4 DDQ SSQ 5 SSQ SSQ 10 SSQ DDQ 11 DDQ /DNU CY7C1383D ...
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... A A TMS TDI TCK TDO CY7C1383F ( ADSP ADSC ADV CLK BWE DQP MODE NC/36M A TMS TDI TCK TDO CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F DDQ A NC/576M A NC/1G DQP DDQ DDQ DDQ DQP NC/36M DDQ DDQ NC/576M A A NC/1G DQP DDQ DDQ DDQ ...
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... B DDQ N DQP DDQ P NC NC/72M A R MODE NC/36M A Document #: 38-05544 Rev. *F CY7C1381D (512K x 36 BWE CLK TDO A TDI A0 A TCK TMS CY7C1383D ( BWE CLK TDI A1 TDO TCK TMS CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F ADSC ADV ADSP A NC/576M V V NC/1G DQP SS DDQ ...
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... When ADSP and ADSC are both [1:0] are also loaded into the burst counter. When ADSP and ADSC are both [1:0] and DQP s is controlled by BW correspondingly CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F [ and CE are sampled active and BWE). [A:D] is HIGH. CE ...
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... CE ) and latched and written into the device. Byte writes are allowed. All IOs are tri-stated during a byte write. As this is a common IO device, the asynchronous OE input signal must be CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F DD through a pull This pin is not DD [ and CE are all ...
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... Linear Burst Address Table (MODE = GND) First Address A1 and can follow [1: Test Conditions ZZ > V – 0. > V – 0. < 0.2V This parameter is sampled This parameter is sampled CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F [ ADSP, and ADSC must after the ZZ input ZZREC ) DD Second Third Fourth Address Address Address A1: A0 A1: A0 A1: A0 ...
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... CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F ADV WRITE OE CLK L-H Tri-State L-H Tri-State L-H Tri-State L-H Tri-State L-H Tri-State Tri-State L L-H Tri-State L L L-H Tri-State L L-H Tri-State L L-H Tri-State L-H Tri-State L L-H Tri-State L L Writes may occur only on subsequent clocks after X Page ...
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... B B Write All Bytes Write All Bytes Note: 9. Table only lists a partial listing of the byte write combinations. Any combination of BW Document #: 38-05544 Rev BWE BWE , valid. Appropriate write will be done based on which byte write is active. X CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Page [+] Feedback ...
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... When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary ‘01’ pattern to allow for fault isolation of the board level serial test path. CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F TAP Controller Block TAP Controller State Diagram.) ...
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... When this scan cell, called the “extest output bus tri-state,” is latched into the preload register during the Update-DR state in the TAP controller, it will directly control the state of the output CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F ). The SRAM clock input might not be CH Page ...
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... TAP controller is in the Test-Logic-Reset state. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions CYC TL t TMSS t TMSH t TDIS t TDIH t TDOV t TDOX DON’T CARE UNDEFINED Description / ns CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F 5 6 Min Max Unit MHz ...
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... OL DDQ I = 100 µ 3.3V OL DDQ V = 2.5V DDQ V = 3.3V DDQ V = 2.5V DDQ V = 3.3V DDQ V = 2.5V DDQ GND < V < DDQ CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F to 2.5V SS 1.25V 50Ω Ω 20pF O Min Max Unit 2.4 V 2.0 V 2.9 V 2.1 V 0.4 V 0.4 V 0.2 V 0 0.3 ...
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... Bit Size (×36 Description CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Description Describes the version number. Reserved for internal use. Defines the memory type and architecture. Defines the memory type and architecture. Defines the width and density. Allows unique identification of SRAM vendor. ...
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... BGA Boundary Scan Order Bit # Ball ID Bit # Notes: 14. Balls which are NC (No Connect) are pre-set LOW. 15. Bit pre-set HIGH. Document #: 38-05544 Rev. *F CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F [14, 15] Ball ID Bit # Ball Bit # Ball Internal Page [+] Feedback ...
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... R11 12 H11 13 N11 14 M11 15 L11 16 K11 17 J11 18 M10 19 L10 20 K10 21 J10 H10 24 G11 25 F11 26 E11 27 D11 28 G10 29 F10 30 E10 Note: 16. Bit pre-set HIGH. Document #: 38-05544 Rev. *F CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F [14, 16] Bit # Ball ID 31 D10 32 C11 33 A11 34 B11 35 A10 36 B10 C10 ...
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... Device Deselected, All Speeds DD ≥ V ≤ 0.3V, – 0. /2), undershoot: V (AC) > –2V (pulse width less than t CYC IL (min) within 200 ms. During this time V < V and CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F + 0.5V DD Ambient DDQ 3.3V –5%/+10% 2.5V – Min Max Unit 3.135 3.6 V 3.135 ...
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... DDQ OUTPUT GND 351Ω INCLUDING JIG AND (b) SCOPE R = 1667Ω 2.5V V DDQ OUTPUT GND 1538Ω INCLUDING JIG AND (b) SCOPE CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F 119 BGA 165 FBGA Package Package Unit 119 BGA 165 FBGA Package Package Unit 23.8 20.7 ° ...
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... V AC Test Loads and Waveforms on page and t is less than t to eliminate bus contention between SRAMs when sharing the same OELZ CHZ CLZ CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F 100 MHz Max Min Max Unit ...
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... On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH. Document #: 38-05544 Rev ADS t ADH ADVH ADVS ADV suspends burst t CDV t OELZ t DOH Q(A2 BURST READ DON’T CARE UNDEFINED CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Deselect Cycle t CHZ Q( Q(A2 Burst wraps around to its initial state Page [+] Feedback ...
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... Full width write can be initiated by either GW LOW HIGH, BWE LOW and BW Document #: 38-05544 Rev. *F ADSC extends burst WES WEH ADV suspends burst D(A2 BURST WRITE DON’T CARE UNDEFINED LOW. X CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F t ADS t ADH A3 t WES t WEH t ADVS t ADVH D( D(A3 Extended BURST WRITE Page [+] Feedback ...
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... The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC. 29 HIGH. Document #: 38-05544 Rev WES WEH OELZ D(A3) t CDV Q(A4) Q(A4+1) Single WRITE BURST READ DON’T CARE UNDEFINED CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F A5 A6 D(A5) D(A6) Q(A4+2) Q(A4+3) Back-to-Back WRITEs Page [+] Feedback ...
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... ALL INPUTS (except ZZ) Outputs (Q) Notes: 30. Device must be deselected when entering ZZ mode. See 31. DQs are in high-Z when exiting ZZ sleep mode. Document #: 38-05544 Rev. *F CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F t RZZI DESELECT or READ Only High-Z DON’T CARE [ Truth Table on page 9 for all possible signal conditions to deselect the device. ...
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... Fine-Pitch Ball Grid Array ( 1.4 mm) CY7C1383D-133BZC CY7C1381D-133BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array ( 1.4 mm) Pb-Free CY7C1383D-133BZXC CY7C1381D-133AXI 51-85050 100-Pin Thin Quad Flat Pack ( 1.4 mm) Pb-Free CY7C1383D-133AXI CY7C1381F-133BGI 51-85115 119-ball Ball Grid Array ( 2.4 mm) CY7C1383F-133BGI CY7C1381F-133BGXI 51-85115 119-ball Ball Grid Array ( 2.4 mm) Pb-Free CY7C1383F-133BGXI CY7C1381D-133BZI 51-85180 165-ball Fine-Pitch Ball Grid Array ( ...
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... BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3. DIMENSIONS IN MILLIMETERS A CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F 1.40±0.05 12°±1° A SEE DETAIL (8X) ...
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... Package Diagrams (continued) Figure 2. 119-ball BGA ( 2.4 mm) (51-85115) Document #: 38-05544 Rev. *F CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F 51-85115-*B Page [+] Feedback ...
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... SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD) JEDEC REFERENCE : MO-216 / DESIGN 4.6C PACKAGE WEIGHT : 0.475g PACKAGE CODE : BB0AC JEDEC REFERENCE : MO-216 / DESIGN 4.6C PACKAGE CODE : BB0AC CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F BOTTOM VIEW PIN 1 CORNER BOTTOM VIEW PIN 1 CORNER Ø0. Ø0. Ø0. Ø ...
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... Document History Page Document Title: CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM Document Number: 38-05544 Orig. of REV. ECN NO. Issue Date Change ** 254518 See ECN *A 288531 See ECN *B 326078 See ECN *C 351895 See ECN *D 416321 See ECN *E 475009 See ECN *F 776456 See ECN Document #: 38-05544 Rev ...