PSD834F2V-15M STMicroelectronics, PSD834F2V-15M Datasheet - Page 58

IC FLASH 2MBIT 150NS 52QFP

PSD834F2V-15M

Manufacturer Part Number
PSD834F2V-15M
Description
IC FLASH 2MBIT 150NS 52QFP
Manufacturer
STMicroelectronics
Datasheet

Specifications of PSD834F2V-15M

Format - Memory
FLASH
Memory Type
FLASH
Memory Size
2M (256K x 8)
Speed
150ns
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
52-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-2011

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PSD834F2V-15M
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
PSD834F2V-15M
Manufacturer:
ST
0
PSD813F2V, PSD854F2V
Input Macrocells (IMC)
The Input Macrocells (IMC) can be used to latch or
store external inputs. The outputs of the Input
Macrocells (IMC) are routed to the PLD input bus,
and can be read by the MCU. See the section en-
titled
Enable Out
The Enable Out register can be read by the MCU.
It contains the output enable values for a given
port. A 1 indicates the driver is in output mode. A
0 indicates the driver is in tri-state and the pin is in
input mode.
Figure 28. Port A and Port B Structure
58/109
PLDS, page
33.
ALE
ADDRESS
MACROCELL OUTPUTS
WR
WR
WR
ENABLE PRODUCT TERM ( .OE )
CONTROL REG.
CPLD-INPUT
DATA OUT
READ MUX
DIR REG.
G
D
D
D
D
REG.
P
D
B
Q
Q
Q
Q
Doc ID 10552 Rev 3
A [ 7:0 ] OR A [ 15:8 ]
ADDRESS
Ports A and B – Functionality and Structure
Ports A and B have similar functionality and struc-
ture, as shown in Figure 28. The two ports can be
configured to perform one or more of the following
functions:
DATA OUT
DATA IN
MCU I/O Mode
CPLD Output – Macrocells McellAB7-
McellAB0 can be connected to Port A or Port
B. McellBC7-McellBC0 can be connected to
Port B or Port C.
CPLD Input – Via the Input Macrocells (IMC).
Latched Address output – Provide latched
address output as per
Address In – Additional high address inputs
using the Input Macrocells (IMC).
Open Drain/Slew Rate – pins PA3-PA0 and
PB3-PB0 can be configured to fast slew rate,
pins PA7-PA4 and PB7-PB4 can be
configured to Open Drain Mode.
Data Port – Port A to D7-D0 for 8 bit non-
multiplexed bus
Multiplexed Address/Data port for certain
types of MCU bus interfaces.
Peripheral Mode – Port A only
OUTPUT
SELECT
OUTPUT
MUX
ENABLE OUT
MACROCELL
INPUT
Table 21., page
A OR B PIN
PORT
54.
AI02887

Related parts for PSD834F2V-15M