W7100A-64QFN WIZnet, W7100A-64QFN Datasheet - Page 21
W7100A-64QFN
Manufacturer Part Number
W7100A-64QFN
Description
8-bit Microcontrollers - MCU 8051 CORE+HARDWIRED TCP/IP+MAC+PHY
Manufacturer
WIZnet
Datasheet
1.W7100A.pdf
(156 pages)
Specifications of W7100A-64QFN
Rohs
yes
Interface Type
UART
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P2.7
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
Note: User can control the GPIO I/O driving voltage using PxPU/PxPD SFR.
Note: In that case, GPIO0~3 is used to transfer External memory address and data. Please
refer to the ‘2.3 External Data Memory Access’
1.4.2.7 External Memory Interface
Pin name
ALE
nWR
nRD
Note: When user using External memory by standard 8051 interface, P0[7:0] can transfer
Data[7:0] or Address[7:0] by ALE pin control.
1.4.2.8 Media Interface
Pin name
TXON
TXOP
RXIN
RXIP
RESETBG
For the best performance,
1. Make the length of RXIP / RXIN signal pair (RX) same if possible.
2. Make the length of TXOP / TXON signal pair (TX) same if possible.
3. Locate the RXIP and RXIN signal as near as possible.
100pin
Pin number
99
34
35
37
39
40
41
42
43
52
53
55
56
59
Num
78
79
80
64pin
32
33
35
36
38
-
-
-
-
-
-
-
-
-
I/O Type
O
OL
OL
I/O
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
O
I
I
I
Pu/Pd
-
-
-
-
-
-
-
-
-
Description
Data memory address bus [7:0] latch enable
External data memory write
External data memory read
-
-
-
-
-
Port2 input/output, Ext Memory Addr15
Port3 input/output, Ext Memory Addr16
Port3 input/output, Ext Memory Addr17
Port3 input/output, Ext Memory Addr18
Port3 input/output, Ext Memory Addr19
Port3 input/output, Ext Memory Addr20
Port3 input/output, Ext Memory Addr21
Port3 input/output, Ext Memory Addr22
Port3 input/output, Ext Memory Addr23
Description
TXON/TXOP Signal Pair, The differential data is
transmitted to the media on the TXON/TXOP
signal pair
RXIN/RXIP Signal Pair, The differential data from
the media is received on the RXIN/RXIP Signal
pair
PHY Off-chip resistor, Connect a resistor of 12.3
㏀±1% to the ground. Refer to the “Reference
schematic”
Ver. 1.12
21
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