W7100A-64QFN WIZnet, W7100A-64QFN Datasheet - Page 108
W7100A-64QFN
Manufacturer Part Number
W7100A-64QFN
Description
8-bit Microcontrollers - MCU 8051 CORE+HARDWIRED TCP/IP+MAC+PHY
Manufacturer
WIZnet
Datasheet
1.W7100A.pdf
(156 pages)
Specifications of W7100A-64QFN
Rohs
yes
Interface Type
UART
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9
standalone without other devices to Ethernet application. In this section, both the
initialization of the W7100A and the communication method for each protocol (TCP, UDP,
IPRAW and MACRAW) based on Pseudo code will be introduced.
9.1
information and the internal TX/RX memory.
1. Interrupt setting
2. Memory Access timing setting
3. Serial baud rate, register and interrupt setting for serial communication
1) For the serial communication, related registers of W7100A should be set.
Since the W7100A internally contains the 8051 compatible MCU and TCP/IP core, it can run
The initialization of W7100A has three steps which setup the 8051 MCU, the network
STEP 1 : Initializes MCU
Set the enable / disable state of interrupt such as the general 8051. Detail information
of the setting refers to the section 3 ‘Interrupt’.
The memory access timing can be set by using two registers which are CKCON (0x8E) and
WTST (0x92) registers. The CKCON (0x8E) can control the data memory access timing and
the WTST (0x92) can control the code memory access timing. Both two registers can set
their value from 0 to 7. But in the W7100A, CKCON can set the value 1~7 and WTST can
set the value 4~7 only. The other values of both registers are not used. If the user sets
the value to an unused value, the W7100A cannot run properly. Detail information can be
found in the section 2.5 ‘SFR definition’.
The registers of W7100A for serial communication are TMOD, PCON and SCON as below.
① TMOD(89H): Decide the timer/counter mode for serial communication.
GATE
Functional Description
Initialization
Ex) Setting: interrupt disabled, 2 clocks access time with data memory, 7 clocks
access time with code memory.
EA = 0;
CKCON = 0x01;
WTST = 0x06;
C/T
M
1
M
// Disable all interrupts
// Set data memory access time
// Set code memory access time
0
GATE
C/T
M
1
Ver. 1.12
M
0
108
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