W7100A-64QFN WIZnet, W7100A-64QFN Datasheet - Page 47
W7100A-64QFN
Manufacturer Part Number
W7100A-64QFN
Description
8-bit Microcontrollers - MCU 8051 CORE+HARDWIRED TCP/IP+MAC+PHY
Manufacturer
WIZnet
Datasheet
1.W7100A.pdf
(156 pages)
Specifications of W7100A-64QFN
Rohs
yes
Interface Type
UART
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4
P0[7:0]
P1[7:0]
P2[7:0]
P3[7:0]
(0x80), P1 (0x90), P2 (0xA0), and P3 (0xB0). Some port-reading instructions read from the
data registers while others read from the port pin. The “Read-Modify-Write” instructions are
directed to the data registers as shown below.
The I/O port pin functionalities are described in the following table.
Read and write accesses are performed in the I/O ports via their corresponding SFR: P0
Pin
P0.7
P1.7
P2.7
P3.7
7
7
7
7
I/O Ports
Active
-
-
-
-
P0.6
P1.6
P2.6
P3.6
6
6
6
6
Type
IO
IO
IO
IO
P0.5
P1.5
P2.5
P3.5
5
5
5
5
Table 4.1 I/O Ports Pin Description
Pu/Pd
Figure 4.1 Port0 Register
Figure 4.2 Port1 Register
Figure 4.3 Port2 Register
Figure 4.4 Port3 Register
P0.4
P1.4
P2.4
P3.4
-
-
-
-
4
4
4
4
P2 (0xA0)
P3 (0xB0)
P0 (0x80)
P1 (0x90)
P0.3
P1.3
P2.3
P3.3
3
3
3
3
P0.2
P1.2
P2.2
P3.2
2
2
2
2
Port0 input / output
Port1 input / output
Port2 input / output
Port3 input / output
Description
P0.1
P1.1
P2.1
P3.1
1
1
1
1
P0.0
P1.0
P2.0
P3.0
Ver. 1.12
0
0
0
0
Reset
Reset
Reset
Reset
0xFF
0xFF
0xFF
0xFF
47
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