CY7C1357C-100AXC Cypress Semiconductor Corp, CY7C1357C-100AXC Datasheet - Page 22

• Manufacturer Part Number: CY7C1357C-100AXC
• Description: IC SRAM 9MBIT 100MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Synchronousr

Specifications of CY7C1357C-100AXC

• Memory Size: 9M (512K x 18)
• Package / Case: 100-LQFP
• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: 7.5 ns
• Maximum Clock Frequency: 100 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Current: 180 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Ports: 2
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Switching Characteristics
Over the Operating Range
Document Number: 38-05539 Rev. *H
t
Clock
t
t
t
Output Times
t
t
t
t
t
t
t
Set-up Times
t
t
t
t
t
t
Hold Times
t
t
t
t
t
t
Notes
POWER
CYC
CH
CL
CDV
DOH
CLZ
CHZ
OEV
OELZ
OEHZ
AS
ALS
WES
CENS
DS
CES
AH
ALH
WEH
CENH
DH
CEH
16. Timing reference level is 1.5 V when V
17. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
18. This part has a voltage regulator internally; t
19. t
20. At any given voltage and temperature, t
21. This parameter is sampled and not 100% tested.
Parameter
can be initiated.
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve high Z prior to low Z under the same system conditions.
CHZ
, t
CLZ
,t
OELZ
, and t
OEHZ
V
Clock cycle time
Clock HIGH
Clock LOW
Data output valid after CLK rise
Data output hold after CLK rise
Clock to low Z
Clock to high Z
OE LOW to output valid
OE LOW to output low Z
OE HIGH to output high Z
Address set-up before CLK rise
ADV/LD set-up before CLK rise
WE, BW
CEN set-up before CLK rise
Data input set-up before CLK rise
Chip enable set-up before CLK rise
Address hold after CLK rise
ADV/LD hold after CLK rise
WE, BW
CEN hold after CLK rise
Data input hold after CLK rise
Chip enable hold after CLK rise
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
DD
[16, 17]
(typical) to the first access
X
X
DDQ
OEHZ
set-up before CLK rise
hold after CLK rise
POWER
= 3.3 V and is 1.25 V when V
is less than t
[19, 20, 21]
[19, 20, 21]
is the time that the power needs to be supplied above V
Description
OELZ
[19, 20, 21]
[19, 20, 21]
and t
[18]
CHZ
is less than t
DDQ
= 2.5 V.
CLZ
to eliminate bus contention between SRAMs when sharing the same
Min
7.5
3.0
3.0
2.0
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
1
–
0
–
–
0
–
–133
DD
(minimum) initially, before a read or write operation
Max
6.5
3.5
3.5
3.5
CY7C1355C, CY7C1357C
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Min
4.0
4.0
2.0
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
10
1
–
0
–
–
0
–
–100
Max
7.5
3.5
3.5
3.5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Page 22 of 32
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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