CY7C1357C-133AXI Cypress Semiconductor Corp, CY7C1357C-133AXI Datasheet

IC SRAM 9MBIT 133MHZ 100LQFP

CY7C1357C-133AXI

Manufacturer Part Number
CY7C1357C-133AXI
Description
IC SRAM 9MBIT 133MHZ 100LQFP
Manufacturer
Cypress Semiconductor Corp
Type
Synchronousr
Datasheet

Specifications of CY7C1357C-133AXI

Memory Size
9M (512K x 18)
Package / Case
100-LQFP
Format - Memory
RAM
Memory Type
SRAM - Synchronous
Speed
133MHz
Interface
Parallel
Voltage - Supply
3.135 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Access Time
6.5 ns
Maximum Clock Frequency
133 MHz
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3.135 V
Maximum Operating Current
250 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Number Of Ports
2
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C1357C-133AXI
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Part Number:
CY7C1357C-133AXIT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Cypress Semiconductor Corporation
Document #: 38-05539 Rev. *E
Features
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Note:
• No Bus Latency™ (NoBL™) architecture eliminates
• Can support up to 133-MHz bus operations with zero
• Pin compatible and functionally equivalent to ZBT™
• Internally self-timed output buffer control to eliminate
• Registered inputs for flow-through operation
• Byte Write capability
• 3.3V/2.5V I/O power supply (V
• Fast clock-to-output times
• Clock Enable (CEN) pin to enable clock and suspend
• Synchronous self-timed writes
• Asynchronous Output Enable
• Available in JEDEC-standard and lead-free 100-Pin
• Three chip enables for simple depth expansion.
• Automatic Power-down feature available using ZZ
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• Burst Capability—linear or interleaved burst order
• Low standby power
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
dead cycles between write and read cycles
wait states
— Data is transferred on every clock
devices
the need to use OE
— 6.5 ns (for 133-MHz device)
operation
TQFP, lead-free and non lead-free 119-Ball BGA
package and 165-Ball FBGA package
mode or CE deselect
Flow-Through SRAM with NoBL™ Architecture
DDQ
)
198 Champion Court
133 MHz
250
6.5
40
Functional Description
The CY7C1355C/CY7C1357C is a 3.3V, 256K x 36/512K x 18
Synchronous Flow-through Burst SRAM designed specifically
to support unlimited true back-to-back Read/Write operations
without
CY7C1355C/CY7C1357C is equipped with the advanced No
Bus Latency (NoBL) logic required to enable consecutive
Read/Write operations with data being transferred on every
clock cycle. This feature dramatically improves the throughput
of data through the SRAM, especially in systems that require
frequent Write-Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).
Write operations are controlled by the two or four Byte Write
Select (BW
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
9-Mbit (256K x 36/512K x 18)
San Jose
the
X
) and a Write Enable (WE) input. All writes are
insertion
,
CA 95134-1709
100 MHz
180
7.5
40
[1]
of
Revised September 14, 2006
wait
1
, CE
CY7C1355C
CY7C1357C
2
, CE
states.
408-943-2600
Unit
mA
mA
ns
3
) and an
The
[+] Feedback

Related parts for CY7C1357C-133AXI

CY7C1357C-133AXI Summary of contents

Page 1

... For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05539 Rev. *E 9-Mbit (256K x 36/512K x 18) Functional Description The CY7C1355C/CY7C1357C is a 3.3V, 256K x 36/512K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the ...

Page 2

... REGISTER MODE CE CLK C CEN WRITE ADDRESS ADV/ READ LOGIC CE1 CE2 CE3 SLEEP ZZ CONTROL 2 Logic Block Diagram – CY7C1357C (512K x 18) ADDRESS A0, A1, A REGISTER MODE CE CLK C CEN WRITE ADDRESS ADV/ READ LOGIC CE1 CE2 CE3 SLEEP ZZ CONTROL Document #: 38-05539 Rev A1' ...

Page 3

... Pin Configurations DQP DDQ BYTE DDQ Vss/DNU DDQ BYTE DDQ DQP 30 D Document #: 38-05539 Rev. *E 100-Pin TQFP Pinout CY7C1355C CY7C1355C CY7C1357C 80 DQP DDQ BYTE DDQ DDQ BYTE DDQ DQP A Page [+] Feedback ...

Page 4

... Pin Configurations (continued DDQ DDQ Vss/DNU BYTE DDQ DQP DDQ Document #: 38-05539 Rev. *E 100-Pin TQFP Pinout CY7C1357C CY7C1355C CY7C1357C DDQ DQP DDQ BYTE DDQ DDQ Page [+] Feedback ...

Page 5

... NC R NC/144M T NC/72M U V DDQ Document #: 38-05539 Rev. *E CY7C1355C (256K x 36 NC/18M ADV/ DQP CLK CEN DQP MODE NC/72M TMS TDI TCK TDO CY7C1357C (512K x 18 NC/18M ADV/ CLK CEN DQP MODE NC/36M A TMS TDI TCK TDO CY7C1355C CY7C1357C DDQ DQP DQ ...

Page 6

... NC B DDQ DDQ DDQ DDQ N DQP DDQ P NC/144M NC/72M A R MODE NC/36M A Document #: 38-05539 Rev. *E CY7C1355C (256K x 36 CEN CLK TDI A1 TDO TCK TMS CY7C1357C (512K x 18 CEN CLK TDI A1 TDO TCK TMS CY7C1355C CY7C1357C ADV/ NC/18M DQP SS DDQ DDQ DDQ V ...

Page 7

... CE to select/deselect the device and CE to select/deselect the device and CE to select/deselect the device and DQP s is controlled by BW correspondingly left floating selects interleaved burst sequence. DD CY7C1355C CY7C1357C are placed in a tri-state condition.The X . During s through a pull up resistor. DD Page [+] Feedback ...

Page 8

... Read/Modify/Write sequences, which can be reduced to simple Byte Write operations. Because the CY7C1355C/CY7C1357C is a common I/O device, data should not be driven into the device while the outputs are active. The Output Enable (OE) can be deasserted HIGH before presenting data to the DQs and DQP Doing so will tri-state the output drivers ...

Page 9

... X the data portion of a write cycle, regardless of the state of OE. Burst Write Accesses The CY7C1355C/CY7C1357C has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Write operations without reasserting the address inputs. ADV/LD must be driven LOW in order to load the initial address, as described in the Single Write Access section above ...

Page 10

... Write Byte C – (DQ and DQP ) C C Write Byte D – (DQ and DQP ) D D Write All Bytes [2, 3,9] Truth Table for Read/Write Function (CY7C1357C) Read Write - No bytes written Write Byte A – (DQ and DQP ) A A Write Byte B – (DQ and DQP ) B B Write All Bytes Note: 9 ...

Page 11

... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1355C/CY7C1357C incorporates a serial boundary scan test access port (TAP) in the BGA package only. The TQFP package does not offer this functionality. This part operates in accordance with IEEE Standard 1149.1-1900, but doesn’t have the set of functions required for full 1149.1 compliance ...

Page 12

... This instruction also selects the boundary scan register to be connected for serial access between the TDI and TDO in the shift-DR controller state. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. CY7C1355C CY7C1357C Page [+] Feedback ...

Page 13

... CS CH 11. Test conditions are specified using the load in TAP AC Test Conditions. t Document #: 38-05539 Rev CYC TL t TMSS t TMSH t TDIS t TDIH t TDOX DON’T CARE UNDEFINED [10, 11] Over the Operating Range Description / ns CY7C1355C CY7C1357C TDOV Min. Max. Unit MHz ...

Page 14

... Defines memory type and architecture 100110 010110 Defines width and density 00000110100 00000110100 Allows unique identification of SRAM vendor 1 1 Indicates the presence register CY7C1355C CY7C1357C to 2.5V SS 1.25V 50Ω 50Ω 20pF O < +70° 3.3V ± 0.165V unless A DD Min. Max. ...

Page 15

... RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. Document #: 38-05539 Rev. *E Bit Size (x36) Bit Size (x18 Description CY7C1355C CY7C1357C Page [+] Feedback ...

Page 16

... Internal DQP Document #: 38-05539 Rev. *E CY7C1357C (512K x 18) Signal Signal Name Bit# ball Id Name A 1 CLK CEN MODE 5 B4 ADV/LD DQP Internal Internal Internal Internal Internal Internal DQP Internal Internal Internal C DQP 24 Internal Internal Internal Internal A 26 Internal Internal CE 27 Internal ...

Page 17

... DQP 24 Internal Internal Internal Internal R11 R10 P10 CY7C1355C CY7C1357C CY7C1357C (512K x 18) Signal Signal Name Bit# ball ID Name CLK CEN ADV/ MODE A 42 Internal Internal A 43 Internal Internal A 44 Internal Internal A 45 Internal Internal Internal 46 N1 DQP B Internal Internal 48 L1 ...

Page 18

... DD ≥ V ≤ inputs /2), undershoot: V (AC) > –2V (Pulse width less than t CYC IL (min.) within 200 ms. During this time V < V and CY7C1355C CY7C1357C + 0.5V DD Ambient Temperature DDQ 0°C to +70°C 3.3V – 5%/+10% 2.5V – Min. Max. Unit 3.135 3.6 3.135 V DD 2.375 2 ...

Page 19

... EIA/JESD51 317Ω 3.3V V DDQ GND 351Ω INCLUDING JIG AND (b) SCOPE R = 1667Ω 2.5V V DDQ GND 1538Ω INCLUDING JIG AND (b) SCOPE CY7C1355C CY7C1357C 119 BGA 165 FBGA Max. Max. Unit 119 BGA 165 FBGA Package Package Unit °C/W 34 ...

Page 20

... DDQ is the time that the power needs to be supplied above V and t is less than t to eliminate bus contention between SRAMs when sharing the same OELZ CHZ CLZ CY7C1355C CY7C1357C –133 –100 Max. Min. Max. Unit 4 ...

Page 21

... D(A2) D(A2+1) Q(A3) Q(A4) t OEHZ BURST READ READ BURST WRITE Q(A3) Q(A4) READ D(A2+1) Q(A4+1) DON’T CARE UNDEFINED is LOW. When CE is HIGH HIGH CY7C1355C CY7C1357C OEV t CHZ Q(A4+1) D(A5) Q(A6) D(A7) t DOH t OELZ WRITE READ WRITE DESELECT D(A5) Q(A6) D(A7) is LOW HIGH ...

Page 22

... Document #: 38-05539 Rev CDV t DOH t OEV t CLZ D(A2) D(A2+1) Q(A3) Q(A4) t OEHZ BURST READ READ BURST WRITE Q(A3) Q(A4) READ Q(A4+1) DON’T CARE UNDEFINED CY7C1355C CY7C1357C CHZ Q(A4+1) D(A5) Q(A6) D(A7) t DOH t OELZ WRITE READ WRITE DESELECT D(A5) Q(A6) D(A7) Page [+] Feedback ...

Page 23

... Notes: 26. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device. 27. DQs are in high-Z when exiting ZZ sleep mode. Document #: 38-05539 Rev ZZREC t RZZI DESELECT or READ Only High-Z DON’T CARE CY7C1355C CY7C1357C Page [+] Feedback ...

Page 24

... Fine-Pitch Ball Grid Array ( 1.4 mm) CY7C1357C-133BZC CY7C1355C-133BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array ( 1.4 mm) Lead-Free CY7C1357C-133BZXC CY7C1355C-133AXI 51-85050 100-Pin Thin Quad Flat Pack ( 1.4 mm) Lead-Free CY7C1357C-133AXI CY7C1355C-133BGI 51-85115 119-ball Ball Grid Array ( 2.4 mm) CY7C1357C-133BGI CY7C1355C-133BGXI 51-85115 119-ball Ball Grid Array ( 2.4 mm) Lead-Free CY7C1357C-133BGXI CY7C1355C-133BZI 51-85180 165-ball Fine-Pitch Ball Grid Array ( ...

Page 25

... BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3. DIMENSIONS IN MILLIMETERS A CY7C1355C CY7C1357C 1.40±0.05 12°±1° A SEE DETAIL (8X) ...

Page 26

... Package Diagrams (continued) A1 CORNER 0.70 REF. 12.00 30° TYP. SEATING PLANE C Document #: 38-05539 Rev. *E 119-Ball BGA ( 2.4 mm) (51-85115) Ø1.00(3X) REF 0.15(4X) CY7C1355C CY7C1357C Ø0. Ø0. Ø0.75±0.15(119X 1.27 3.81 7.62 14.00±0.20 51-85115-*B Page [+] Feedback ...

Page 27

... PACKAGE WEIGHT : 0.475g SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD) JEDEC REFERENCE : MO-216 / DESIGN 4.6C PACKAGE WEIGHT : 0.475g PACKAGE CODE : BB0AC JEDEC REFERENCE : MO-216 / DESIGN 4.6C PACKAGE CODE : BB0AC CY7C1355C CY7C1357C BOTTOM VIEW PIN 1 CORNER BOTTOM VIEW PIN 1 CORNER Ø0. Ø0. Ø0. Ø ...

Page 28

... Document History Page Document Title: CY7C1355C/CY7C1357C 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL™ Architecture Document Number: 38-05539 Orig. of REV. ECN NO. Issue Date Change ** 242032 See ECN *A 332059 See ECN *B 351895 See ECN *C 377095 See ECN *D 408298 See ECN *E 501793 See ECN Document #: 38-05539 Rev ...

Related keywords