CY7C1357C-100AXC Cypress Semiconductor Corp, CY7C1357C-100AXC Datasheet

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... K × 18 synchronous flow-through burst SRAM designed specifically to support unlimited true back-to-back read/write operations without CY7C1355C/CY7C1357C is equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive read/write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent write-read transitions ...

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... MODE CE CLK C CEN WRITE ADDRESS ADV/ READ LOGIC CE1 CE2 CE3 SLEEP ZZ CONTROL Document Number: 38-05539 Rev A1 A0 BURST ADV/LD LOGIC C REGISTER WRITE WRITE REGISTRY DRIVERS AND DATA COHERENCY CONTROL LOGIC CY7C1355C, CY7C1357C MEMORY ARRAY DQs F T DQP DQP DQP DQP ...

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... Logic Block Diagram – CY7C1357C (512 K × 18) ADDRESS A0, A1, A REGISTER MODE CE CLK C CEN ADV/ READ LOGIC CE1 CE2 CE3 SLEEP ZZ CONTROL Document Number: 38-05539 Rev A1 A0 BURST ADV/LD LOGIC C WRITE ADDRESS REGISTER WRITE WRITE REGISTRY DRIVERS AND DATA COHERENCY CONTROL LOGIC ...

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... TAP AC Switching Characteristics ............................... 15 3.3 V TAP AC Test Conditions ....................................... 16 3.3 V TAP AC Output Load Equivalent ......................... 16 2.5 V TAP AC Test Conditions ....................................... 16 2.5 V TAP AC Output Load Equivalent ......................... 16 Document Number: 38-05539 Rev. *H CY7C1355C, CY7C1357C TAP DC Electrical Characteristics and Operating Conditions ..................................................... 16 Identification Register Definitions ................................ 16 Scan Register Sizes ....................................................... 17 Identification Codes ....................................................... 17 119-ball BGA Boundary Scan Order ...

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... Maximum CMOS standby current Pin Configurations DQP DDQ BYTE DDQ Vss/DNU DDQ BYTE DDQ DQP 30 D Document Number: 38-05539 Rev. *H CY7C1355C, CY7C1357C 133 MHz 6.5 250 40 100-pin TQFP Pinout CY7C1355C 100 MHz Unit 7.5 ns 180 DQP DDQ BYTE DDQ DDQ BYTE ...

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... Pin Configurations (continued DDQ DDQ Vss/DNU BYTE DDQ DQP DDQ Document Number: 38-05539 Rev. *H CY7C1355C, CY7C1357C 100-pin TQFP Pinout CY7C1357C DDQ DQP DDQ BYTE DDQ DDQ Page [+] Feedback ...

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... NC R NC/144M NC/72M DDQ Document Number: 38-05539 Rev. *H CY7C1355C (256 K × 36 NC/18M ADV/ DQP CLK CEN DQP MODE NC/72M TMS TDI TCK TDO CY7C1357C (512 K × 18 NC/18M ADV/ CLK CEN DQP MODE NC/36M A TMS TDI TCK TDO CY7C1355C, CY7C1357C DDQ DQP DQ B ...

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... V B DDQ DDQ DDQ N DQP DDQ P NC/144M NC/72M A R MODE NC/36M A Document Number: 38-05539 Rev. *H CY7C1355C (256 K × 36 CEN CLK TDI A1 TDO TCK TMS CY7C1357C (512 K × 18 CEN CLK TDO A TDI A A0 TCK TMS CY7C1355C, CY7C1357C ADV/ NC/18M DQP SS DDQ DDQ ...

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... CE to select/deselect the device and CE to select/deselect the device and CE to select/deselect the device and DQP s is controlled by BW correspondingly left floating selects interleaved burst sequence. DD CY7C1355C, CY7C1357C are placed in a tri-state condition.The X . During s through a pull-up DD Page [+] Feedback ...

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... This pin is not available on TQFP packages. SS Burst Read Accesses The CY7C1355C/CY7C1357C has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four reads without reasserting the address inputs. ADV/LD must be driven LOW in order to load a new address into the SRAM, as described in the above ...

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... X write cycle, regardless of the state of OE. Burst Write Accesses The CY7C1355C/CY7C1357C has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four write operations without reasserting the address inputs. ADV/LD must be driven LOW in order to load the initial ...

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... L H None Next Current None [ data when OE is active valid. Appropriate write will be done based on which byte write is active. X CY7C1355C, CY7C1357C OE CEN CLK L->H Tri-state L->H Tri-state L->H Tri-state L->H Tri-state L->H Data out ( L->H Data out ( L->H Tri-state L->H Tri-state L-> ...

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... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1355C/CY7C1357C incorporates a serial boundary scan test access port (TAP) in the BGA package only. The TQFP package does not offer this functionality. This part operates in accordance with IEEE Standard 1149.1-1900, but doesn’t have the set of functions required for full 1149.1 compliance. These ...

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... Once the data is captured possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. CY7C1355C, CY7C1357C ). The SRAM clock input might not be CH Page [+] Feedback ...

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... Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions CYC TL t TMSS t TMSH t TDIS t TDIH t TDOX DON’T CARE UNDEFINED Description / ns CY7C1355C, CY7C1357C TDOV Min Max Unit 50 – ns – 20 MHz 20 – – ns – – ...

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... Reserved for Internal Use 001001 001001 Defines memory type and architecture 100110 010110 Defines width and density 00000110100 00000110100 Allows unique identification of SRAM vendor 1 1 Indicates the presence register CY7C1355C, CY7C1357C to 2 1.25V 50Ω 50Ω 20pF O Min Max Unit 2.4 – ...

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... Do Not Use: This instruction is reserved for future use. RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. Document Number: 38-05539 Rev. *H CY7C1355C, CY7C1357C Bit Size (× 36) Bit Size (× 18 Description ...

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... Internal DQP Document Number: 38-05539 Rev. *H CY7C1357C (512 K × 18) Signal Signal Bit# ball Id Name Name A 1 CLK CEN MODE 5 B4 ADV/LD DQP Internal Internal Internal Internal Internal Internal DQP Internal Internal Internal C DQP 24 Internal Internal Internal Internal A 26 Internal Internal CE 27 ...

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... C DQP 24 Internal Internal Internal Internal R11 R10 P10 CY7C1355C, CY7C1357C CY7C1357C (512 K × 18) Signal Signal Bit# ball ID Name Name CLK CEN ADV/ MODE A 42 Internal Internal A 43 Internal Internal A 44 Internal Internal A 45 Internal Internal Internal 46 N1 DQP B Internal Internal 48 L1 ...

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... Max, device deselected, All speeds ≥ V ≤ inputs /2), undershoot: V (AC) > –2 V (Pulse width less than t CYC IL (min) within 200 ms. During this time V < V and CY7C1355C, CY7C1357C Ambient DDQ Temperature 3.3 V 2.5 V – 5% – 10 –40 ° +85 °C Min Max Unit 3.135 3 ...

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... EIA/JESD51 317 Ω 3 DDQ GND 351 Ω INCLUDING JIG AND (b) SCOPE R = 1667 Ω 2 DDQ GND 1538 Ω INCLUDING JIG AND (b) SCOPE CY7C1355C, CY7C1357C 119 BGA 165 FBGA Unit Max Max 119 BGA 165 FBGA Unit Package Package °C/W 34 ...

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... V. DDQ is the time that the power needs to be supplied above V and t is less than t to eliminate bus contention between SRAMs when sharing the same OELZ CHZ CLZ CY7C1355C, CY7C1357C –100 Unit Max Min Max – 1 – ms – 10 – ...

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... CLZ t OEV D(A2) D(A2+1) Q(A3) Q(A4) t OEHZ BURST READ READ BURST WRITE Q(A3) Q(A4) READ Q(A4+1) DON’T CARE UNDEFINED is LOW. When CE is HIGH HIGH CY7C1355C, CY7C1357C CHZ Q(A4+1) D(A5) Q(A6) D(A7) t DOH t OELZ WRITE READ WRITE DESELECT D(A5) Q(A6) D(A7) is LOW HIGH ...

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... DOH t OEV t CLZ Q(A3) Q(A4) D(A2+1) t OEHZ t OELZ READ READ BURST Q(A3) Q(A4) READ Q(A4+1) DON’T CARE UNDEFINED is LOW. When CE is HIGH HIGH CY7C1355C, CY7C1357C CHZ Q(A4+1) D(A5) Q(A6) D(A7) t DOH WRITE READ WRITE DESELECT D(A5) Q(A6) D(A7) is LOW HIGH ...

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... Outputs (Q) Notes 28. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device. 29. DQs are in high Z when exiting ZZ sleep mode. Document Number: 38-05539 Rev. *H CY7C1355C, CY7C1357C t ZZREC t RZZI DESELECT or READ Only High-Z DON’T CARE ...

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... Speed Grade (133 MHz / 100 MHz) Process Technology ≥ 90nm 135X = 1355 / 1357 1355 = FT, 256 Kb × Mb) 1357 = FT, 512 Kb × Mb) CY7C = Cypress SRAMs Document Number: 38-05539 Rev. *H CY7C1355C, CY7C1357C www.cypress.com and refer to the product Part and Package Type Operating Range Commercial Commercial ...

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... Package Diagrams 100-pin Thin Plastic Quad Flatpack (14 × 20 × 1.4 mm), 51-85050 Document Number: 38-05539 Rev. *H CY7C1355C, CY7C1357C 51-85050 *D Page [+] Feedback ...

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... Package Diagrams (continued) Document Number: 38-05539 Rev. *H 119-ball BGA (14 × 22 × 2.4 mm), 51-85115 CY7C1355C, CY7C1357C 51-85115 *C Page [+] Feedback ...

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... Package Diagrams (continued) 165-ball FBGA (13 × 15 × 1.4 mm), 51-85180 Document Number: 38-05539 Rev. *H CY7C1355C, CY7C1357C 51-85180 *C Page [+] Feedback ...

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... TDI test data input TMS test mode select TDO test data output TQFP thin quad flat pack WE write enable Document Number: 38-05539 Rev. *H CY7C1355C, CY7C1357C Document Conventions Units of Measure Symbol Unit of Measure ns nano seconds V Volts µA micro Amperes mA milli Amperes ...

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... Updated Ordering Information and added Added Acronyms and Units of Measure. Minor edits and updated in new template. NJY Removed following pruned parts from ordering information table. CY7C1355C-133BGC CY7C1357C-100AXC Updated package diagram spec 51-85050 to *D. CY7C1355C, CY7C1357C ≥ V ≤ 0.3V ≥ V – 0. < V < ...

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... Document Number: 38-05539 Rev. *H NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All product and company names mentioned in this document are the trademarks of their respective holders cypress.com/go/plc Revised April 1, 2011 CY7C1355C, CY7C1357C PSoC Solutions psoc.cypress.com/solutions PSoC 1 | ...