CY62128EV30LL-45ZXI Cypress Semiconductor Corp, CY62128EV30LL-45ZXI Datasheet
CY62128EV30LL-45ZXI
Specifications of CY62128EV30LL-45ZXI
CY62128EV30LL-45ZXI
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CY62128EV30LL-45ZXI Summary of contents
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... Note 1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at Cypress Semiconductor Corporation Document #: 38-05579 Rev. *I 1-Mbit (128 K × 8) Static RAM Functional Description The CY62128EV30 module organized as 128 K words by 8-bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ ...
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Contents Pin Configuration ............................................................. 3 Product Portfolio .............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 Data Retention Characteristics ....................................... 5 Switching Characteristics ................................................ 6 Switching Waveforms ...................................................... ...
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... Top View (not to scale Product Portfolio Product Range Min CY62128EV30LL Industrial Notes 2. NC pins are not connected on the die. 3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V Document #: 38-05579 Rev I/O ...
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... CMOS level to meet the Document #: 38-05579 Rev input voltage [4, 5] Output current into outputs (LOW) .............................. 20 mA Static discharge voltage.......................................... > 2001 V (MIL-STD-883, method 3015) Latch-up current ..................................................... > 200 mA Operating Range + 0.3 V Device CC(max) CY62128EV30LL + 0.3 V CC(max) Test Conditions I = –0 –1.0 mA, V > 2. 0.1 mA ...
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Capacitance Parameter Description [9] C Input capacitance Output capacitance OUT Thermal Resistance Parameter [9] Description Thermal resistance Still air, soldered 4.5 inch, JA (junction to ambient) two-layer printed circuit board ...
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... HZOE HZCE HZWE 17. The internal write time of the memory is defined by the overlap of WE terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write. Document #: 38-05579 Rev. *I Figure 5. Data Retention Waveform ...
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... DATA I/O NOTE t HZOE Notes 18. The internal write time of the memory is defined by the overlap of WE terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write. 19. The device is continuously selected HIGH for read cycle. ...
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... Notes 26 the logical combination of CE and CE . When 27. The internal write time of the memory is defined by the overlap of WE write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write. 28. Data I/O is high impedance 29 goes HIGH or CE goes LOW simultaneously with WE HIGH, the output remains in high impedance state ...
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... Ordering Information Speed Ordering Code (ns) 45 CY62128EV30LL-45SXI CY62128EV30LL-45ZXI CY62128EV30LL-45ZAXI Contact your local Cypress sales representative for availability of these parts. Ordering Code Definitions CY 621 8 E V30 Document #: 38-05579 Rev. *I Package Package Type Diagram 51-85081 32-pin 450-Mil SOIC (Pb-free) 51-85056 32-pin TSOP Type I (Pb-free) ...
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Package Diagrams Figure 11. 32-pin (450 Mil) Molded SOIC, 51-85081 Document #: 38-05579 Rev. *I ® CY62128EV30 MoBL 51-85081 *C Page [+] Feedback ...
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Package Diagrams (continued) Figure 12. 32-pin Thin Small Outline Package Type mm), 51-85056 Document #: 38-05579 Rev. *I ® CY62128EV30 MoBL 51-85056 *E Page [+] Feedback ...
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Package Diagrams (continued) Figure 13. 32-pin Shrunk Thin Small Outline Package (8 x 13.4 mm), 51-85094 Document #: 38-05579 Rev. *I ® CY62128EV30 MoBL 51-85094 *E Page [+] Feedback ...
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... Acronym Description CMOS complementary metal oxide semiconductor CE chip enable I/O input/output OE output enable SRAM static random access memory TSOP thin small outline package STSOP shrunk thin small outline package SOIC small outline integrated circuit WE write enable Document Conventions Units of Measure Symbol ...
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... Changed the Maximum rating of Ambient Temperature with Power Applied from 55°C to +125°C to –55°C to +125°C. Corrected “t ” spec description in the “Switching Characteristics” table. PD VKN Included “CY62128EV30LL-45ZAXA” part in the Ordering Information table VKN Added footnote #21 related to chip enable Updated package diagrams Updated template AJU ...
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... Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement ...