LHF00L28 Sharp Microelectronics, LHF00L28 Datasheet - Page 16

• Manufacturer Part Number: LHF00L28
• Description: IC FLASH 16MBIT 70NS 48TSOP
• Manufacturer: Sharp Microelectronics

Specifications of LHF00L28

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 16M (1M x 16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 425-1885

SR.7 = WRITE STATE MACHINE STATUS (WSMS)
(R)
SR.15 - SR.8 = RESERVED FOR FUTURE
SR.6 = BLOCK ERASE SUSPEND STATUS (BESS)
SR.5 = BLOCK ERASE AND FULL CHIP ERASE
SR.4 = PROGRAM AND
SR.3 = WP#/ACC STATUS (WPACCS)
SR.2 = PROGRAM SUSPEND
SR.1 = DEVICE PROTECT STATUS (DPS)
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS
ENHANCEMENTS (R)
WSMS
1 = Ready
0 = Busy
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
1 = Error in Block Erase or Full Chip Erase
0 = Successful Block Erase or Full Chip Erase
1 = Error in Program or OTP Program
0 = Successful Program or OTP Program
1 = V
0 = WP#/ACC OK
1 = Program Suspended
0 = Program in Progress/Completed
1 = Erase or Program Attempted on a
0 = Unlocked
15
R
7
Operation Abort
Locked Block, Operation Abort
STATUS (BEFCES)
STATUS (PSS)
OTP PROGRAM STATUS (POPS)
CC
+0.4V < WP#/ACC < 11.7V Detect,
BESS
14
R
6
BEFCES
13
R
5
Table 8. Status Register Definition
POPS
12
R
4
LHF00L28
Status Register indicates the status of the WSM (Write State
Machine).
Check SR.7 or RY/BY# to determine block erase, full chip
erase, program or OTP program completion. SR.6 - SR.1 are
invalid while SR.7="0".
If both SR.5 and SR.4 are "1"s after a block erase, full chip
erase, program, set/clear block lock bit, set block lock-down
bit attempt, an improper command sequence was entered.
SR.3 does not provide a continuous indication of WP#/ACC
level. The WSM interrogates and indicates the WP#/ACC
level only after Block Erase, Full Chip Erase, Program or
OTP Program command sequences. SR.3 is not guaranteed to
report accurate feedback when WP#/ACC≠V
SR.1 does not provide a continuous indication of block lock
bit. The WSM interrogates the block lock bit only after Block
Erase, Full Chip Erase, Program or OTP Program command
sequences. It informs the system, depending on the attempted
operation, if the block lock bit is set. Reading the block lock
configuration codes after writing the Read Identifier Codes/
OTP command indicates block lock bit status.
SR.15 - SR.8 and SR.0 are reserved for future use and should
be masked out when polling the status register.
WPACCS
11
R
3
PSS
10
R
2
NOTES:
DPS
R
9
1
ACCH
Rev. 2.45
.
R
R
8
0
13