CY7C199CN-15PXC Cypress Semiconductor Corp, CY7C199CN-15PXC Datasheet

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... The device features an automatic power consumption when deselected. See the “Truth Table” on page 3 complete description of read and write modes. The CY7C199CN is available in Pb-free 28-pin TSOP I, 28-pin Molded SOJ and 28-pin DIP package(s). Input Buffer RAM Array Power Column Decoder Down ...

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... Pin Layout and Specifications 28 DIP Document #: 001-06435 Rev TSOP 13.4 mm CY7C199CN 28 SOJ Page [+] Feedback ...

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... WE IOx X High-Z H Data Out L Data In H High-Z Selected, Outputs Disabled Description 0°C to 70°C –40°C to 85°C CY7C199CN SOJ TSOP 10, 11, 12, 13, 14, 15, 16, 17 18, 19, 20, 22, 23, 24, 25, 18 Mode Power Deselect/Power Down Stand Read Active (I ...

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... CE  –  V  max  V – 0.3V, –  V  0.3V – 0.3V Output Disabled – CC – CC CY7C199CN –12 –15 Unit Min Max Min Max 2 0 –0.5 0.8 –0.5 0.8 V 2.4 – 2.4 – V – 0.4 – 0.4 V – ...

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... Tested initially and after any design or process change that may affect these parameters. Document #: 001-06435 Rev. *D Conditions T = 25° MHz 5. Conditions TSOP I Still air, soldered × 4.5 88.6 square inch, two–layer printed circuit board 21. jig ita Description CY7C199CN Max Unit SOJ DIP Unit 79 69.33 °C/W 41.42 31. & ...

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...  V  0.3V V – 0. less than less than t , and t HZCE LZCE HZOE LZOE “” on page 1. Transitions are measured ± 200 mV from steady state voltage. CY7C199CN –20 –25 Unit Min Max Min Max 20 – 25 – ns – 20 – – 3 – ...

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... WE is HIGH for read cycle. 11. This cycle is OE controlled and WE is HIGH read cycle. 12. Address valid before or similar with CE transition LOW. Document #: 001-06435 Rev. *D DATA RETENTION MODE OHA ACE t DOE t LZOE t LZCE t PU 50% CY7C199CN t R Data Valid t HZCE t HZOE High Z Data Valid t PD 50% Page [+] Feedback ...

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... During this period the IOs are in output state and input signals must not be applied. 16. This cycle is CE controlled. 17 goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. Document #: 001-06435 Rev SCE PWE t SD Data-In Valid SCE Data-In Valid . CY7C199CN High Z Page [+] Feedback ...

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... Write Cycle 3 (WE controlled, OE low) Address Data Undefined In Out see footnotes Note 18. The cycle is WE controlled, OE LOW. The minimum write cycle time is the sum of t Document #: 001-06435 Rev SCE PWE Data In Valid t HZWE and t . HZWE SD CY7C199CN t HA Undefined See Footnotes t LZWE Page [+] Feedback ...

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... Ordering Information Contact local sales representative regarding availability of these parts. Speed Package Ordering Code (ns) Diagram 12 CY7C199CN-12VXA 51-85031 15 CY7C199CN-15PXC 51-85014 CY7C199CN-15VXC 51-85031 CY7C199CNL-15VXI 51-85031 20 CY7C199CN-20ZXI 51-85071 Ordering Code Definitions Document #: 001-06435 Rev. *D Package Type 28-Lead (300-Mil) Molded SOJ, Pb-free 28 DIP (6.9 x 35.6 x 3.5 mm), Pb-free ...

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... Package Diagrams Figure 1. 28-pin TSOP 13.4 mm), 51-85071 Document #: 001-06435 Rev. *D CY7C199CN 51-85071 *H Page [+] Feedback ...

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... Package Diagrams (continued) Figure 2. 28-pin (300 Mil) Molded SOJ, 51-85031 Document #: 001-06435 Rev. *D CY7C199CN 51-85031 *D Page [+] Feedback ...

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... Package Diagrams (continued) All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 001-06435 Rev. *D Figure 3. 28-pin (300 Mil) PDIP, 51-85014 CY7C199CN 51-85014 *E Page [+] Feedback ...

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... Document History Page Document Title: CY7C199CN, 256K (32K x 8) Static RAM Document Number: 001-06435 Issue REV. ECN No. Date ** 430363 See ECN *A 684342 See ECN *B 839904 See ECN *C 2896044 03/19/2010 *D 3108898 12/13/2010 Document #: 001-06435 Rev. *D © Cypress Semiconductor Corporation, 2006-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product ...