C8051F591-IMR Silicon Labs, C8051F591-IMR Datasheet - Page 134
C8051F591-IMR
Manufacturer Part Number
C8051F591-IMR
Description
8-bit Microcontrollers - MCU 50 MIPS 96 kB 8 kB SPI 2xUART
Manufacturer
Silicon Labs
Datasheet
1.C8051F585-IQR.pdf
(356 pages)
Specifications of C8051F591-IMR
Rohs
yes
Core
8051
Data Bus Width
8 bit
Processor Series
C8051
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C8051F58x/F59x
SFR Definition 14.5. EIE2: Extended Interrupt Enable 2
SFR Address = 0xE7; SFR Page = All Pages
134
Name
Reset
Bit
Type
7
6
5
4
3
2
1
0
Bit
ECAN0
EREG0
EPCA1
Name
EMAT
ECP2
ET5
ET4
ES1
R/W
ET5
7
0
Enable Timer 5 Interrupt.
This bit sets the masking of the Timer 5 interrupt.
0: Disable Timer 5 interrupts.
1: Enable interrupt requests generated by the TF5L or TF5H flags.
Enable Timer 4 Interrupt.
This bit sets the masking of the Timer 4 interrupt.
0: Disable Timer 4 interrupts.
1: Enable interrupt requests generated by the TF4L or TF4H flags.
Enable Comparator2 (CP2) Interrupt.
This bit sets the masking of the CP2 interrupt.
0: Disable CP2 interrupts.
1: Enable interrupt requests generated by the CP2RIF or CP2FIF flags.
Enable Programmable Counter Array (PCA1) Interrupt.
This bit sets the masking of the PCA1 interrupts.
0: Disable all PCA1 interrupts.
1: Enable interrupt requests generated by PCA1
Enable UART1 Interrupt.
This bit sets the masking of the UART1 interrupt.
0: Disable UART1 interrupt.
1: Enable UART1 interrupt
Enable Port Match Interrupt.
This bit sets the masking of the Port Match interrupt.
0: Disable all Port Match interrupts.
1: Enable interrupt requests generated by a Port Match
Enable CAN0 Interrupts.
This bit sets the masking of the CAN0 interrupt.
0: Disable all CAN0 interrupts.
1: Enable interrupt requests generated by CAN0.
Enable Voltage Regulator Dropout Interrupt.
This bit sets the masking of the Voltage Regulator Dropout interrupt.
0: Disable the Voltage Regulator Dropout interrupt.
1: Enable the Voltage Regulator Dropout interrupt.
R/W
ET4
6
0
ECP2
R/W
5
0
EPCA1
R/W
Rev. 1.2
4
0
Function
R/W
ES1
3
0
EMAT
R/W
2
0
ECAN0
R/W
1
0
EREG0
R/W
0
0
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