C8051F572-IMR Silicon Labs, C8051F572-IMR Datasheet - Page 199
C8051F572-IMR
Manufacturer Part Number
C8051F572-IMR
Description
8-bit Microcontrollers - MCU 50 MIPS 16 kB 2 kB CAN2.0 LIN 2.1 SPI
Manufacturer
Silicon Labs
Datasheet
1.C8051F556-IMR.pdf
(302 pages)
Specifications of C8051F572-IMR
Rohs
yes
Core
8051
Data Bus Width
8 bit
Processor Series
C8051
- Current page: 199 of 302
- Download datasheet (2Mb)
SFR Definition 20.3. LIN0CF: LIN0 Control Mode Register
SFR Address = 0xC9; SFR Page = 0x0F
Name
Reset
Bit
4:0
Type
7
6
5
Bit
ABAUD
Unused
LINEN
MODE
LINEN
Name
R/W
7
0
MODE
LIN Interface Enable Bit.
0: LIN0 is disabled.
1: LIN0 is enabled.
LIN Mode Selection Bit.
0: LIN0 operates in slave mode.
1: LIN0 operates in master mode.
LIN Mode Automatic Baud Rate Selection.
This bit only has an effect when the MODE bit is configured for slave mode.
0: Manual baud rate selection is enabled.
1: Automatic baud rate selection is enabled.
Read = 00000b; Write = Don’t Care
R/W
6
1
ABAUD
R/W
5
1
R
4
0
Rev. 1.1
Function
R
3
0
C8051F55x/56x/57x
R
2
0
R
1
0
R
0
0
199
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