IS42S32800D-7TL ISSI, Integrated Silicon Solution Inc, IS42S32800D-7TL Datasheet - Page 25
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IS42S32800D-7TL
Manufacturer Part Number
IS42S32800D-7TL
Description
IC SDRAM 256MBIT 143MHZ 86TSOP
Manufacturer
ISSI, Integrated Silicon Solution Inc
Type
SDRAMr
Specifications of IS42S32800D-7TL
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
256M (8Mx32)
Speed
143MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
86-TSOPII
Organization
8Mx32
Density
256Mb
Address Bus
13b
Access Time (max)
6.5/5.4ns
Maximum Clock Rate
143MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
150mA
Pin Count
86
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
706-1084
IS42S32800D-7TL
IS42S32800D-7TL
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IS42S32800D-7TL
Manufacturer:
TRACO
Quantity:
101
Part Number:
IS42S32800D-7TL
Manufacturer:
ISSI
Quantity:
20 000
Part Number:
IS42S32800D-7TLI
Manufacturer:
ISSI
Quantity:
20 000
CAS LATENCY
IS42S32800D, IS45S32800D
CAS Latency
The CAS latency is the delay, in clock cycles, between
the registration of a READ command and the availability of
the first piece of output data. The latency can be set to two or
three clocks.
If a READ command is registered at clock edge n, and
the latency is m clocks, the data will be available by clock
edge n + m. The DQs will start driving as a result of the
clock edge one cycle earlier (n + m - 1), and provided that
the relevant access times are met, the data will be valid by
clock edge n + m. For example, assuming that the clock
cycle time is such that all relevant access times are met,
if a READ command is registered at T0 and the latency
is programmed to two clocks, the DQs will start driving
after T1 and the data will be valid by T2, as shown in CAS
Latency diagrams. The Allowable Operating Frequency
table indicates the operating frequencies at which each
CAS latency setting can be used.
Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
Integrated Silicon Solution, Inc. - www.issi.com
Rev. C
12/01/09
COMMAND
COMMAND
CLK
CLK
DQ
DQ
READ
READ
T0
T0
CAS Latency - 2
NOP
NOP
CAS Latency - 3
T1
T1
t
LZ
t
AC
CAS Latency
Operating Mode
The normal operating mode is selected by setting M7 and M8
to zero; the other combinations of values for M7 and M8 are
reserved for future use and/or test modes. The programmed
burst length applies to both READ and WRITE bursts.
Test modes and reserved states should not be used be-
cause unknown operation or incompatibility with future
versions may result.
Write Burst Mode
When M9 = 0, the burst length programmed via M0-M2
applies to both READ and WRITE bursts; when M9 = 1,
the programmed burst length applies to READ bursts, but
write accesses are single-location (nonburst) accesses.
Speed
-75E
NOP
NOP
Allowable Operating Frequency (MHz)
T2
T2
-6
-7
D
OUT
t
t
OH
LZ
t
AC
NOP
T3
T3
CAS Latency = 2
D
DON'T CARE
UNDEFINED
OUT
t
OH
100
100
133
T4
CAS Latency = 3
166
143
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