IS62WV12816DBLL-45TLI-TR ISSI, IS62WV12816DBLL-45TLI-TR Datasheet - Page 10

• Manufacturer Part Number: IS62WV12816DBLL-45TLI-TR
• Description: SRAM 2Mb 128K x 1645ns Async SRAM
• Manufacturer: ISSI

Specifications of IS62WV12816DBLL-45TLI-TR

• Rohs: yes
• Memory Size: 2 Mbit
• Organization: 128 Kbit x 16
• Access Time: 45 ns
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.5 V
• Maximum Operating Current: 21 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: TSOP-44
• Memory Type: CMOS
• Factory Pack Quantity: 1000

IS62WV12816DALL/DBLL, IS65WV12816DALL/DBLL
WRITE CYCLE SWITCHING CHARACTERISTICS
Notes:
1. Test conditions and output loading conditions are specified in the AC Test Conditions and AC Test Loads (Figure 1).
2. The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH and UB or LB, and WE LOW. All signals must be in
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
10
Symbol
t
t
t
t
t
t
t
t
t
t
t
valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are
referenced to the rising or falling edge of the signal that terminates the write.
Wc
ScS1/
AW
HA
SA
PWB
PWe
Sd
Hd
HzWe
LzWe
(3)
t
(3)
ScS2
Parameter
Write Cycle Time
CS1/CS2 to Write End
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
LB, UB Valid to End of Write
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
Min.
35
25
25
30
30
15
—
0
0
0
5
35 ns
Max.
20
—
—
—
—
—
—
—
—
—
—
(1,2)
(Over Operating Range)
Integrated Silicon Solution, Inc. — www.issi.com
Min.
45
35
35
35
35
20
—
0
0
0
5
45 ns
Max.
20
—
—
—
—
—
—
—
—
—
—
Min.
55
45
45
45
40
25
—
0
0
0
5
55 ns
Max.
20
—
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2/4/2013
Rev. B