70V3319S133BF IDT, 70V3319S133BF Datasheet - Page 5

• Manufacturer Part Number: 70V3319S133BF
• Description: SRAM 256Kx18 STD-PWR 3.3V SYNC DUAL-PORT RAM
• Manufacturer: IDT

Specifications of 70V3319S133BF

• Part # Aliases: IDT70V3319S133BF

Pin Names
R/W
I/O
CLK
PIPE/FT
CE
OE
A
ADS
CNTEN
REPEAT
UB
LB
0L
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
0L
0L
L
L
L
L
L
- A
L
,
Left Port
- I/O
CE
V
17L
OPT
L
L
DDQL
L
1L
(5)
17L
(1)
L
TRST
TDO
TMS
V
V
TCK
TDI
DD
SS
R/W
I/O
CLK
PIPE/FT
CE
OE
A
ADS
CNTEN
REPEAT
UB
LB
0R
R
0R
0R
R
R
R
R
Right Port
- A
R
,
- I/O
CE
V
OPT
17R
R
R
DDQR
R
1R
(5)
17R
(1)
R
Chip Enables
Read/Write Enable
Output Enable
Data Input/Output
Clock
Pipeline/Flow-Through
Counter Enable
Counter Repeat
Upper Byte Enable (I/O
Lower Byte Enable (I/O
Power (I/O Bus) (3.3V or 2.5V)
Option for selecting V
Power (3.3V)
Ground (0V)
Reset (Initialize TAP Controller)
Address
Address Strobe Enable
Test Data Input
Test Data Output
Test Logic Clock (10MHz)
Test Mode Select
(2)
(6)
Names
(4)
DDQX
0
9
-I/O
-I/O
(2,3)
8
17
)
5623 tbl 01
(6)
)
(6)
(2)
6.42
5
NOTES:
1. A
2. V
3. OPT
4. When REPEAT
5. PIPE/FT option in PK-128 package is not supported due to limitation in pin count.
6. Chip Enables and Byte Enables are double buffered when PL/FT = V
applying inputs on the I/Os and controls for that port.
If OPT
levels and V
port's I/Os and address controls will operate at 2.5V levels and V
supplied at 2.5V. The OPT pins are independent of one another—both ports can
operate at 3.3V levels, both can operate at 2.5V levels, or either can operate
at 3.3V with the other at 2.5V.
via ADS
Device is pipelined output mode only on each port.
signals take two cycles to deselect.
DD
17
, OPT
X
is a NC for IDT70V3399.
selects the operating voltage levels for the I/Os and controls on that port.
X
is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V
X
.
X
, and V
DDQX
X
is asserted, the counter will reset to the last valid address loaded
Industrial and Commercial Temperature Ranges
must be supplied at 3.3V. If OPT
DDQX
must be set to appropriate operating levels prior to
X
is set to VIL (0V), then that
DDQX
IH
, i.e., the
must be