IS42S16100E-7TL ISSI, Integrated Silicon Solution Inc, IS42S16100E-7TL Datasheet - Page 19

• Manufacturer Part Number: IS42S16100E-7TL
• Description: IC SDRAM 16MBIT 143MHZ 50TSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: SDRAMr

Specifications of IS42S16100E-7TL

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 16M (1M x 16)
• Speed: 143MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 50-TSOPII
• Organization: 1Mx16
• Density: 16Mb
• Address Bus: 12b
• Access Time (max): 6/5.5ns
• Maximum Clock Rate: 143MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 130mA
• Pin Count: 50
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 706-1071; IS42S16100E-7TL

IS42S16100E, IC42S16100E
TWO BANKS OPERATION COMMAND TRUTH TABLE
Notes:
1. H: HIGH level input, L: LOW level input, X: HIGH or LOW level input, RA: Row Address, CA: Column Address
2. The device state symbols are interpreted as follows:
3. CA: A8,A9 = don’t care.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08
Operation
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF
MRS
I
A
R
W
RP
WP
Any Any State
Idle (inactive state)
Row Active State
Read
Write
Read With Auto-Precharge
Write With Auto-Precharge
CS RAS CAS WE A11 A10 A9-A0
H
L
L
L
L
L
L
L
L
H
H
H
H
X
L
L
L
L
H
H
H
H
X
L
L
L
L
H
H
H
H
X
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
OPCODE
RA RA
RA RA
H CA
H CA
H CA
H CA
H CA
H CA
H CA
H CA
H
H
X
X
X
X
L CA
L CA
L CA
L CA
L CA
L CA
L CA
L CA
L
L
L
L
X
X
X
X
X
X
X
X
X
X
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
BANK 0 BANK 1 BANK 0 BANK 1
R/W/A/I
R/W/A/I
R/W/A/I
R/W/A
R/W/A
R/W/A
R/W/A
R/W/A
R/W
R/W
R/W
R/W
Any
Any
Any
I/A
I/A
I/A
I/A
I/A
I/A
I/A
I/A
I/A
A
A
A
A
I
I
I
I
(1,2)
R/W/A/I
R/W/A/I
R/W/A/I
R/W/A
R/W/A
R/W/A
R/W/A
R/W/A
R/W
R/W
R/W
R/W
Previous State
Any
Any
Any
I/A
I/A
I/A
I/A
I/A
I/A
I/A
I/A
I/A
A
A
A
A
I
I
I
I
R/W/A/I
Any
Any
Any
WP
WP
RP
RP
I/A
I/A
I/A
I/A
I/A
I/A
I/A
W
W
A
A
A
R
R
A
A
A
I
I
I
I
I
I
I
R/W/A/I
Any
Any
Any
WP
WP
RP
RP
I/A
I/A
I/A
I/A
I/A
I/A
I/A
W
W
Next State
A
R
R
A
A
A
A
A
I
I
I
I
I
I
I
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