BR93L86-W Rohm Semiconductor, BR93L86-W Datasheet - Page 30

• Manufacturer Part Number: BR93L86-W
• Description: IC EEPROM 16KBIT 2MHZ 8DIP
• Manufacturer: Rohm Semiconductor

Specifications of BR93L86-W

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 16K (1K x 16)
• Speed: 2MHz
• Interface: Microwire, 3-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

●Application
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BR93L□□-W Series, 93A□□-WM Series, BR93H□□-WC Series
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4) Write enable (WEN) / disable (WDS) cycle
1) Method to cancel each command
○At power on, this IC is in write disable status by the internal RESET circuit. Before executing the write command, it is
○When the write enable command is executed after power on, write enable status gets in. When the write disable
○READ
○WRITE, WRAL
necessary to execute the write enable command. And, once this command is executed, it is valid unitl the write disable
command is executed or the power is turned off. However, the read command is valid irrespective of write enable /
disable command. Input to SK after 6 clocks of this command is available by either “H” or “L”, but be sure to input it.
command is executed then, the IC gets in write disable status as same as at power on, and then the write command is
cancelled thereafter in software manner. However, the read command is executable. In write enable status, even when
the write command is input by mistake, write is started. To prevent such a mistake, it is recommended to execute the
write disable command after completion of write.
a ： From start bit to 27 clock rise
b ： 27 clock rise and after *
c ： 28 clock rise and after *
● Method to cancel ： cancel by CS= “ L ”
Start bit
Start bit
Fig.34 READ cancel available timing
1bit
Cancel by CS=“L”
Cancellation is not available by any means. If Vcc is made OFF in this area,
designated address data is not guaranteed, therefore write once again.
Cancel by CS=“L”
However, when write is started in b area (CS is ended), cancellation is not
available by any means.
And when SK clock is input continuously, cancellation is not available.
1bit
Fig.35 WRITE, WRAL cancel available timing
Cancel is available in all areas in read mode.
CS
SK
DI
DO
High-Z
Ope code
Ope code
Fig. 33 Write enable (WEN) / disable (WDS) cycle
2bit
2bit
2
3
1
1
0
2
a
Address
Address
0
3
8bit
8bit
4
*1
*1
5
SK
DI
DISABLE=0 0
ENABLE=1 1
・ Rise of 27clock
6
D1
16bit
Data
16bit
Data
Enlarged figure
7
30/40
26
a
D0
8
27
b
～ ～
～ ～
～ ～
b
～ ～
n
*2
28
*1 Address is 8 bits in BR93H56-WC, and BR93H66-WC.
c
tE/W
29
C
Address is 10 bits in BR93H76-WC, and BR93H86-WC.
Note 1) If Vcc is made OFF in this area,
Note 2) If CS is started at the same timing as that of
*1 Address is 8 bits in BR93H56/66-WC
*2 27 clocks in BR93H56/66-WC
*3 28 clocks in BR93H56/66-WC
designated address data is not guaranteed,
therefore write once again.
the SK rise, write execution/cancel becomes
unstable, therefore, it is recommended to fail in
SK=”L” area. As for SK rise, recommend timing of
tCSS/tCSH or higher.
Address is 10 bits in BR93H76/86-WC
29 clocks in BR93H76/86-WC
30 clocks in BR93H76/86-WC
BR93H56/66-WC : n=11
BR93H76/86-WC : n=13
Technical Note
2011.02 - Rev.F