BR93L86-W Rohm Semiconductor, BR93L86-W Datasheet - Page 14

• Manufacturer Part Number: BR93L86-W
• Description: IC EEPROM 16KBIT 2MHZ 8DIP
• Manufacturer: Rohm Semiconductor

Specifications of BR93L86-W

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 16K (1K x 16)
• Speed: 2MHz
• Interface: Microwire, 3-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

●Application
© 2011 ROHM Co., Ltd. All rights reserved.
BR93L□□-W Series, 93A□□-WM Series, BR93H□□-WC Series
www.rohm.com
1) Method to cancel each command
○READ
○WRITE, WRAL
a：From start bit to 25 clock rise
b：25 clock rise and after
a：From start bit to 29 clock rise
b：29 clock rise and after
c：30 clock rise and after
Fig.66 READ cancel available timing
Cancel by CS=“L”
Cancellation is not available by any means. If Vcc is made OFF in this area,
designated address data is not guaranteed, therefore write once again.
And when SK clock is input continuously, cancellation is not available.
And when SK clock is output continuously is not available.
Cancel by CS=“L”
Cancellation is not available by any means. If Vcc is made OFF in this area,
designated address data is not guaranteed, therefore write once again.
Cancel by CS=“L”
However, when write is started in b area (CS is ended), cancellation is not
available by any means.
・Method to cancel：cancel by CS=“L”
Start bit
Start bit
1bit
1bit
Fig.67 WRITE, WRAL cancel available timing
Start bit
1bit
Cancel is available in all areas in read mode.
Ope code
Ope code
＊
2
2bit
2bit
Ope code
2bit
＊
2
a
a
Address
Address
6bit
6bit
Address
10bit
*1
*1
*1
SK
DI
SK
DI
・25 Rise of clock
29 Rise of clock
D1
D1
Data
16bit
a
16bit
Data
Enlarged figure
Enlarged figure
Data
24
28
14/40
16bit
D0
D0
29
25
b
b
*2
30
＊1 Address is 8 bits in BR93L56-W/A56-WM, BR93L-66W/A66-WM
*2
(In the case of BR93L46-W/A46-WM)
Address is 10 bits in BR93L76-W/A76-WM, BR93L86-W/A86-WM
c
31
*1 Address is 8 bits in BR93L56-W/A56-WM, BR93L66-W/A66-WM
*2 27 clocks in BR93L56-W/A56-WM, BR93L66-W/A66-WM
tE/W
Note 1) If Vcc is made OFF in this area, designated address data is
Note 2) If CS is started at the same timing as that of the SK rise,
tE/W
b
c
Address is 10 bits in BR93L76-W/A76-WM BR93L86-W/A86-WM
29 clocks in BR93L76-W/A76-WM BR93L86-W/A86-WM
not guaranteed, therefore write once again.
write execution/cancel becomes unstable, therefore, it is
recommended to fail in SK=”L” area.
As for SK rise, recommend timing of tCSS/tCSH or higher.
(In the case of BR93L46-W/A46-WM)
(In the case of BR93L86-W/A86-WM)
Technical Note
2011.02 - Rev.F