7130SA55P IDT, 7130SA55P Datasheet - Page 19

• Manufacturer Part Number: 7130SA55P
• Description: SRAM
• Manufacturer: IDT

Specifications of 7130SA55P

• Part # Aliases: IDT7130SA55P

Functional Description
address and I/O pins that permit independent access for reads or
writes to any location in memory. The IDT7130/IDT7140 has an
automatic power down feature controlled by CE. The CE controls on-
chip power down circuitry that permits the respective port to go into a
standby mode when not selected (CE = V
access to the entire memory array is permitted.
Interrupts
box or message center) is assigned to each port. The left port interrupt
flag (INT
3FE (HEX), where a write is defined as the CE
Table II. The left port clears the interrupt by accessing address location
3FE when CE
interrupt flag (INT
3FF (HEX) and to clear the interrupt flag (INT
the memory location 3FF. The message (8 bits) at 3FE or 3FF is user-
defined, since it is an addressable SRAM location. If the interrupt function
is not used, address locations 3FE and 3FF are not used as mail boxes,
but as part of the random access memory. Refer to Truth Table II for the
interrupt operation.
Busy Logic
RAM have accessed the same location at the same time. It also allows
one of the two accesses to proceed and signals the other side that the
RAM is “Busy”. The BUSY pin can then be used to stall the access until
the operation on the other side is completed. If a write operation has
been attempted from the side that receives a BUSY indication, the
write signal is gated internally to prevent the write from proceeding.
tions. In some cases it may be useful to logically OR the BUSY outputs
together and use any BUSY indication as an interrupt source to flag the
event of an illegal or illogical operation. In slave mode the BUSY pin
operates solely as a write inhibit input pin. Normal operation can be
programmed by tying the BUSY pins HIGH. If desired, unintended
write operations can be prevented to a port by tying the BUSY pin for
that port LOW.
type outputs and require open drain resistors to operate. If these
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
The IDT7130/IDT7140 provides two ports with separate control,
If the user chooses the interrupt function, a memory location (mail
Busy Logic provides a hardware indication that both ports of the
The use of BUSY logic is not required or desirable for all applica-
The BUSY outputs on the IDT7130 RAM (Master) are open drain
L
) is asserted when the right port writes to memory location
L
= OE
R
) is asserted when the left port writes to memory location
L =
V
IL,
R/
W is a "don't care". Likewise, the right port
IH
R
). When a port is enabled,
), the right port must access
R
= R/W
R
= V
IL
per Truth
19
270Ω
RAMs are being expanded in depth, then the BUSY indication for the
resulting array does not require the use of an external AND gate.
Width Expansion with Busy Logic
Master/Slave Arrays
master part is used to decide which side of the RAM array will receive
a busy indication, and to output that indication. Any number of slaves
to be addressed in the same address range as the master, use the
busy signal as a write inhibit signal. Thus on the IDT7130/IDT7140
RAMs the BUSY pin is an output if the part is Master (IDT7130), and
the BUSY pin is an input if the part is a Slave (IDT7140) as shown in
Figure 3.
a split decision could result with one master indicating busy on one side
of the array and another master indicating busy on one other side of
the array. This would inhibit the write operations from one port for part
of a word and inhibit the write operations from the other port for the
other part of the word.
address signals only. It ignores whether an access is a read or write.
In a master/slave array, both address and chip enable must be valid
long enough for a BUSY flag to be output from the master before the
actual write pulse can be initiated with either the R/W signal or the byte
enables. Failure to observe this timing can result in a glitched internal
write inhibit signal and corrupted data in the slave.
BUSY
When expanding an RAM array in width while using busy logic, one
If two or more master parts were used when expanding in width,
The BUSY arbitration, on a Master, is based on the chip enable and
Military, Industrial and Commercial Temperature Ranges
5V
Figure 3. Busy and chip enable routing for both width and depth
L
expansion with IDT7130 (Master) and IDT7140 (Slave)RAMs.
MASTER
Dual Port
RAM
BUSY
MASTER
Dual Port
RAM
BUSY
L
L
BUSY
BUSY
CE
CE
R
R
SLAVE
Dual Port
RAM
BUSY
SLAVE
Dual Port
RAM
BUSY
L
L
BUSY
BUSY
CE
CE
R
R
2689 drw 18
BUSY
5V
R
270Ω