7130SA55P IDT, 7130SA55P Datasheet - Page 11

• Manufacturer Part Number: 7130SA55P
• Description: SRAM
• Manufacturer: IDT

Specifications of 7130SA55P

• Part # Aliases: IDT7130SA55P

Timing Waveform of Read Cycle No. 1, Either Side
NOTES:
1. R/W = V
2. t
3. Start of valid data depends on which timing becomes effective last t
Timing Waveform of Read Cycle No. 2, Either Side
CURRENT
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is deaserted first, OE or CE.
3. R/W = V
4.
ADDRESS
DATA
BUSY
DATA
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
BUSY has no relationship to valid output data.
BDD
Start of valid data depends on which timing becomes effective last t
delay is required only in the case where the opposite port is completing a write operation to the same the address location. For simultaneous read operations,
OUT
OUT
OUT
I
CE
OE
I
CC
SS
IH
IH
, CE = V
and OE = V
PREVIOUS DATA VALID
IL
, and is OE = V
IL
, and the address is valid prior to or coincidental with CE transition LOW.
IL
. Address is valid prior to the coincidental with CE transition LOW.
t
OH
t
t
AA
PU
50%
t
LZ
t
(1)
t
ACE
RC
AOE
AOE
, t
t
, t
BDDH
t
ACE
LZ
ACE
t
AOE
(1)
, t
,
t
AA
AA
(2,3)
, and t
, and
(4)
11
t
BDD
BDD
DATA VALID
.
.
Military, Industrial and Commercial Temperature Ranges
VALID DATA
(1)
(3)
t
OH
t
t
PD
HZ
(4)
(2)
t
HZ
50%
(2)
2689 drw 08
2689 drw 09