P5010NXE1QMB Freescale Semiconductor, P5010NXE1QMB Datasheet - Page 99

• Manufacturer Part Number: P5010NXE1QMB
• Description: Processors - Application Specialized P5010 Ext TmpEnc 1600/1200 r2.0
• Manufacturer: Freescale Semiconductor

Specifications of P5010NXE1QMB

• Rohs: yes

For recommended operating conditions, see
JTAG external clock frequency of operation
JTAG external clock cycle time
JTAG external clock pulse width measured at (OV
JTAG external clock rise and fall times
TRST assert time
Input setup times
Input hold times
Output valid times
Output hold times
Note:
1. The symbols used for timing specifications follow the pattern t
2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
3. All outputs are measured from the midpoint voltage of the falling edge of t
2.17.2
This table provides the JTAG AC timing specifications as defined in
This figure provides the AC test load for TDO and the boundary-scan outputs of the device.
Freescale Semiconductor
t
respect to the time data input signals (D) reaching the valid state (V) relative to the t
state or setup time. Also, t
state (X) relative to the t
representation is based on three letters representing the clock of a particular functional. For rise and fall times, the latter convention
is used with the appropriate letter: R (rise) or F (fall).
timings are measured at the pins. All output timings assume a purely resistive 50-Ω load. Time-of-flight delays must be added for
trace lengths, vias, and connectors in the system.
(first two letters of functional block)(reference)(state)(signal)(state)
JTAG AC Timing Specifications
Parameter
P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0
JTG
JTDXKH
Output
clock reference (K) going to the high (H) state. Note that in general, the clock reference symbol
Boundary-scan except USB
Boundary-scan USB only
symbolizes JTAG timing (JT) with respect to the time data input signals (D) reaching the invalid
Figure 29. AC Test Load for the JTAG Interface
Table
Table 56. JTAG AC Timing Specifications
Boundary-scan data
3.
TDI, and TMS
DD
/2)
Z
0
= 50 Ω
TDO
for outputs. For example, t
(first two letters of functional block)(signal)(state)(reference)(state)
t
JTGR
Symbol
t
t
t
t
t
JTDVKH
JTDXKH
JTKHKL
JTKLDV
JTKLDX
t
f
t
TRST
JTG
JTG
/t
Figure 29
JTGF
1
TCLK
R
L
to the midpoint of the signal in question. The output
= 50 Ω
through
JTDVKH
Min
JTG
30
15
25
14
10
—
—
0
0
4
4
0
Figure
symbolizes JTAG device timing (JT) with
clock reference (K) going to the high (H)
OV
DD
32.
/2
Max
33.3
Electrical Characteristics
15
10
—
—
—
—
—
—
—
—
2
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
for inputs and
Note
99
—
—
—
—
—
2
3
3