P5010NXE1QMB Freescale Semiconductor, P5010NXE1QMB Datasheet - Page 136

• Manufacturer Part Number: P5010NXE1QMB
• Description: Processors - Application Specialized P5010 Ext TmpEnc 1600/1200 r2.0
• Manufacturer: Freescale Semiconductor

Specifications of P5010NXE1QMB

• Rohs: yes

Hardware Design Considerations
The sinusoidal jitter in the total jitter tolerance may have any amplitude and frequency in the unshaded region of
3
3.1
This section describes the PLL configuration of the chip.
This device includes 7 PLLs, as follows:
136
For recommended operating conditions, see
Bit error ratio
Unit Interval: 1.25 GBaud
Unit Interval: 3.125 GBaud
Note:
1. Measured at receiver.
2. Refer to RapidIO
3. Total jitter is composed of three components: deterministic jitter, random jitter, and single frequency sinusoidal jitter. The
sinusoidal jitter may have any amplitude and frequency in the unshaded region of
is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.
•
•
•
•
There are 2 selectable core Complex PLLs which generate a core clock from the externally supplied SYSCLK input.
Core complex 0-1 can select from CC1 PLL or CC2 PLL. The frequency ratio between the core Complex PLLs and
SYSCLK is selected using the configuration bits as described in
PLL
The platform PLL generates the platform clock from the externally supplied SYSCLK input. The frequency ratio
between the platform and SYSCLK is selected using the platform PLL ratio configuration bits as described in
Section 3.1.2, “Platform to SYSCLK PLL Ratio.”
The DDR block PLL generates the DDR clock from the externally supplied SYSCLK input (asynchronous mode) or
from the platform clock (synchronous mode). The frequency ratio is selected using the Memory Controller Complex
PLL multiplier/ratio configuration bits as described in
Each of the three SerDes blocks has a PLL which generate a core clock from their respective externally supplied
SD_REF_CLKn/SD_REF_CLKn inputs. The frequency ratio is selected using the SerDes PLL ratio configuration bits
as described in
Hardware Design Considerations
System Clocking
Ratio.” The frequency for each core complex 0-1 is selected using the configuration bits as described in
Parameter
TM
P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0
1×/4× LP Serial Physical Layer Specification for interpretation of jitter specifications.
Section 3.1.6, “Frequency Options.”
Table 98. SGMII Receive AC Timing Specifications (continued)
Table
3.
Symbol
BER
UI
UI
800 – 100 ppm
320 – 100 ppm
Section 3.1.5, “DDR Controller PLL Ratios.”
Min
—
Section 3.1.3, “e5500-64 Core Complex to SYSCLK
Typ
800
320
—
Figure
320 + 100 ppm
800 + 100 ppm
46. The sinusoidal jitter component
10
Max
-12
Freescale Semiconductor
Unit
ps
ps
—
Figure
Table
Note
—
46.
1
1
102.