P5010NXE1QMB Freescale Semiconductor, P5010NXE1QMB Datasheet - Page 62

• Manufacturer Part Number: P5010NXE1QMB
• Description: Processors - Application Specialized P5010 Ext TmpEnc 1600/1200 r2.0
• Manufacturer: Freescale Semiconductor

Specifications of P5010NXE1QMB

• Rohs: yes

Maximum
Maximum
Maximum
Thermal
Thermal
Thermal
Power
Typical
Typical
Typical
Mode
Electrical Characteristics
2.3
The power-down cycle must complete such that power supply values are below 0.4 V before a new power-up cycle can be
started.
If performing secure boot fuse programming per
the system is power cycled (PORESET assertion) or powered down (V
Table
V
after USB_V
2.4
This table shows the power dissipations of the V
clock frequencies versus the core and DDR clock frequencies for the P5020. Note that these numbers are based on design
estimates only and are preliminary. More accurate power numbers are available after the measurement on the silicon is
complete.
62
DD_PL
(MHz)
Core
Freq
2000
1800
1600
5.
and USB_V
Power Down Requirements
Power Characteristics
DD
(MHz)
Freq
Plat
800
700
600
_3P3 is below 1.65 V.
From a system standpoint, if any of the I/O power supplies ramp prior to the V
V
or zero during power-up, and extra current may be drawn by the device.
DD_CB
DD
(MT/s)
DDR
Data
Rate
1333
1300
1200
_1P0 must be ramped down simultaneously. USB_V
P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0
or V
PME/FM
DD_PL
(MHz)
Freq
600
500
450
supplies, the I/Os associated with that I/O supply may drive a logic one
V
SV
Table 6. P5020 Power Dissipation
DD_PL,
1.0
1.0
1.0
(V)
DD
Section 2.2, “Power Up
DD_CA
V
V
DD_CA,
DD_CB,
1.1
1.1
1.1
(V)
, V
DD_CB
NOTE
Junction
, SV
Temp
(°C)
105
105
105
65
65
65
DD,
DD_PL
Sequencing,” it is required that POV
and V
DD
Core and
Platform
Power
ramp down) per the required timing specified in
_1P8_DECAP should starts ramping down only
(W)
16
28
30
14
26
28
13
22
23
DD_PL
1
supply for various operating platform
V
Power
DD_PL
(W)
19
—
—
19
—
—
16
—
—
DD_CA
V
DD_CA
ower
(W)
—
—
—
—
—
—
Freescale Semiconductor
8
7
6
,
P
DD
V
Power
DD_CB
(W)
—
—
—
—
—
—
8
7
6
= GND before
Power
SV
(W)
—
—
—
—
—
—
2
2
2
DD
4, 6,
4, 6,
4, 6,
Note
2,
5,
2,
5,
2,
5,
3
7
3
7
3
7
7
7
7