MCIMX6S6AVM08AB Freescale Semiconductor, MCIMX6S6AVM08AB Datasheet - Page 92

• Manufacturer Part Number: MCIMX6S6AVM08AB
• Description: Processors - Application Specialized i.MX6 Solo rev 1.1
• Manufacturer: Freescale Semiconductor
• Type: Automotive and Infotainment Processorsr

Specifications of MCIMX6S6AVM08AB

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 800 MHz
• Instruction / Data Cache Memory: 32 KB
• Data Ram Size: 128 KB
• Data Rom Size: 96 KB
• Operating Supply Voltage: 1.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: BGA 2240
• Interface Type: I2S, SSI, AC97, ESAI, UARTS, eCSPI, I2C, Ethernet, PWM, SJC, GPIO, KPP, SPDIF
• Memory Type: DDR3
• Minimum Operating Temperature: - 40 C
• Number Of Timers: 2

Electrical Characteristics
92
1
2
3
4
The timings assume the following configuration:
DDR_SEL = (11)b
DSE (drive-strength) = (111)b
For 10 Mbps and 100 Mbps, T
For all versions of RGMII prior to 2.0; This implies that PC board design will require clocks to be routed
such that an additional trace delay of greater than 1.5 ns and less than 2.0 ns will be added to the
associated clock signal. For 10/100, the Max value is unspecified.
Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's
clock domain as long as minimum duty cycle is not violated and stretching occurs for no more than three
Tcyc of the lowest speed transitioned between.
Duty_G
Duty_T
Symbol
T
skewR
Tr/Tf
i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1
3
4
4
Data to clock input skew at receiver
Duty cycle for Gigabit
Duty cycle for 10/100T
Rise/fall time (20–80%)
Table 65. RGMII Signal Switching Specifications
Figure 52. RGMII Transmit Signal Timing Diagram Original
cyc
will scale to 400 ns ±40 ns and 40 ns ±4 ns respectively.
Description
1
Min.
45
40
—
(continued)
1
Max.
0.75
2.6
55
60
Freescale Semiconductor
Unit
ps
ns
%
%