MCIMX6S6AVM08AB Freescale Semiconductor, MCIMX6S6AVM08AB Datasheet - Page 10

• Manufacturer Part Number: MCIMX6S6AVM08AB
• Description: Processors - Application Specialized i.MX6 Solo rev 1.1
• Manufacturer: Freescale Semiconductor
• Type: Automotive and Infotainment Processorsr

Specifications of MCIMX6S6AVM08AB

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 800 MHz
• Instruction / Data Cache Memory: 32 KB
• Data Ram Size: 128 KB
• Data Rom Size: 96 KB
• Operating Supply Voltage: 1.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: BGA 2240
• Interface Type: I2S, SSI, AC97, ESAI, UARTS, eCSPI, I2C, Ethernet, PWM, SJC, GPIO, KPP, SPDIF
• Memory Type: DDR3
• Minimum Operating Temperature: - 40 C
• Number Of Timers: 2

Modules List
10
Block Mnemonic
eCSPI1-4
DCIC-0
DCIC-1
DTCP
CTI-0
CTI-1
CTI-2
CTI-3
CTI-4
CCM
GPC
CTM
SRC
CSU
DAP
CSI
DSI
i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1
Global Power Controller,
System Reset Controller
Display Content Integrity
Cross Trigger Interfaces
Clock Control Module,
Central Security Unit
Cross Trigger Matrix
Debug Access Port
Configurable SPI
MIPI CSI-2 i/f
Block Name
MIPI DSI i/f
Checker
DTCP
Table 2. i.MX 6Solo/6DualLite Modules List (continued)
Clocks, Resets, and
System Control
Power Control
Debug / Trace
Debug / Trace
Automotive IP
Subsystem
Connectivity
Peripherals
Peripherals
Peripherals
Peripherals
Peripherals
Multimedia
Multimedia
Multimedia
Security
These modules are responsible for clock and reset
distribution in the system, and also for the system power
management.
The CSI IP provides MIPI CSI-2 standard camera
interface port. The CSI-2 interface supports from 80
Mbps to 1 Gbps speed per data lane.
The Central Security Unit (CSU) is responsible for
setting comprehensive security policy within the i.MX
6Solo/6DualLite platform.
Cross Trigger Interfaces allows cross-triggering based
on inputs from masters attached to CTIs. The CTI
module is internal to the Cortex-A9 Core Platform.
Cross Trigger Matrix IP is used to route triggering events
between CTIs. The CTM module is internal to the
Cortex-A9 Core Platform.
The DAP provides real-time access for the debugger
without halting the core to:
The DAP also provides debugger access to JTAG scan
chains. The DAP module is internal to the Cortex-A9
Core Platform.
The DCIC provides integrity check on portion(s) of the
display. Each i.MX 6Solo/6DualLite processor has two
such modules.
The MIPI DSI IP provides DSI standard display port
interface. The DSI interface support 80 Mbps to 1 Gbps
speed per data lane.
Provides encryption function according to Digital
Transmission Content Protection standard for traffic
over MLB150.
Full-duplex enhanced Synchronous Serial Interface,
with data rate up to 52 Mbit/s. It is configurable to
support Master/Slave modes, four chip selects to
support multiple peripherals.
• System memory and peripheral registers
• All debug configuration registers
Brief Description
Freescale Semiconductor