MCIMX6S6AVM08AB Freescale Semiconductor, MCIMX6S6AVM08AB Datasheet - Page 107

• Manufacturer Part Number: MCIMX6S6AVM08AB
• Description: Processors - Application Specialized i.MX6 Solo rev 1.1
• Manufacturer: Freescale Semiconductor
• Type: Automotive and Infotainment Processorsr

Specifications of MCIMX6S6AVM08AB

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 800 MHz
• Instruction / Data Cache Memory: 32 KB
• Data Ram Size: 128 KB
• Data Rom Size: 96 KB
• Operating Supply Voltage: 1.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: BGA 2240
• Interface Type: I2S, SSI, AC97, ESAI, UARTS, eCSPI, I2C, Ethernet, PWM, SJC, GPIO, KPP, SPDIF
• Memory Type: DDR3
• Minimum Operating Temperature: - 40 C
• Number Of Timers: 2

4.11.10.6 Synchronous Interfaces to Standard Active Matrix TFT LCD Panels
4.11.10.6.1 IPU Display Operating Signals
The IPU uses four control signals and data to operate a standard synchronous interface:
All synchronous display controls are generated on the base of an internally generated “local start point”.
The synchronous display controls can be placed on time axis with DI’s offset, up and down parameters.
The display access can be whole number of DI clock (Tdiclk) only. The IPP_DATA can not be moved
relative to the local start point. The data bus of the synchronous interface is output direction only.
4.11.10.6.2 LCD Interface Functional Description
Figure 67
signals are shown with negative polarity. The sequence of events for active matrix interface timing is:
Freescale Semiconductor
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•
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VSYNC
HSYNC
IPP_DISP_CLK
HSYNC
DRDY
IPP_DISP_CLK—Clock to display
HSYNC—Horizontal synchronization
VSYNC—Vertical synchronization
DRDY—Active data
DI_CLK internal DI clock is used for calculation of other controls.
IPP_DISP_CLK latches data into the panel on its negative edge (when positive polarity is selected).
In active mode, IPP_DISP_CLK runs continuously.
HSYNC causes the panel to start a new line. (Usually IPP_PIN_2 is used as HSYNC.)
VSYNC causes the panel to start a new frame. It always encompasses at least one HSYNC pulse.
(Usually IPP_PIN_3 is used as VSYNC.)
DRDY acts like an output enable signal to the CRT display. This output enables the data to be
shifted onto the display. When disabled, the data is invalid and the trace is off.
(DRDY can be used either synchronous or asynchronous generic purpose pin as well.)
IPP_DATA
depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure,
i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1
Figure 67. Interface Timing Diagram for TFT (Active Matrix) Panels
LINE 1
1
LINE 2
2
LINE 3
3
LINE 4
LINE n-1
m-1
Electrical Characteristics
LINE n
m
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