E520.03A61AC ELMOS Semiconductor, E520.03A61AC Datasheet - Page 13

• Manufacturer Part Number: E520.03A61AC
• Description: Motor / Motion / Ignition Controllers & Drivers 8x low side driver
• Manufacturer: ELMOS Semiconductor
• Type: Unipolar Stepper Motor Driverr

Specifications of E520.03A61AC

• Rohs: yes
• Product: Stepper Motor Controllers / Drivers
• Operating Supply Voltage: 3.3 V, 5 V
• Supply Current: 5 mA
• Operating Temperature: - 40 C to + 125 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-32
• Number Of Outputs: 8
• Output Current: 300 mA
• Output Voltage: 3 V to 25 V
• Power Dissipation: 2.8 W

The SI and SO terminals of all devices are tied together. There is an individual chip enable (CEB) line to each device.
At most one of these chip enable lines shall be active at any time in order to avoid data bus contention on the SO
line. The protocol frame of the SPI consists of 16 bits. It contains an address identifi er of 4 bits and 12 data bits for
the 12 driver channels or other functions.
The SPI protocol frame is defi ned as follows:
• On the falling edge of the CEB signal the SO data output is going into low impedance state.
• With each rising edge of the clock signal SCLK the data will be shifted out at SO in "MSB fi rst" order, beginning
• With each falling edge of the clock signal SCLK the new input data at SI will be shifted into the SPI register in
• On the rising edge of the CEB signal the content of the SPI shift register will be latched and transferred to the
• The content of the output data DI[11:0] depends on the submitted address bit.
This document contains information on a pre-production product. ELMOS Semiconductor AG reserves the right to change specifi cations and information herein without notice.
12 / 8 CHANNEL LOW SIDE DRIVER WITH STALL DETECTION
PRODUCTION DATA - JUL 24, 2012
ELMOS Semiconductor AG
with four status bits, followed by the data bits DO
"MSB fi rst" order, beginning with the address bits ADR3 down to ADR0, followed by the data bits DI
to DI
output drivers or internal registers, respectively. The SO data output goes back to high impedance state.
0
OUT11
OUT10
SCLK
OUT1
OUT0
SCLK
CEB
CEB
SI
SO
⋮
SI
SO
90%
90%
90%
90%
10%
10%
10%
10%
ADR3
SUP
ADR2
T
OVT
LSO
T
LCF
ADR1
ATT
T
ADR0
CSO
OC
sample
data
⋮
Figure 4. SPI interface Timing Diagram
T
DI11
DO11
DS
DI7
T
DH
DI10
DO10
DO7
Figure 3. SPI Protocol
DI9
DO9
Data Sheet
T
13/29
CSO
OUT11
OUT10
OUT1
OUT0
DI8
DO8
11
⋮
down to DO
T
DS
DI6
DI7
DO7
DO6
T
DH
DI6
DO6
DI5
DO5
0
.
DI4
DO4
DO1
T
CSO
DI3
DO3
T
DS
DI0
DI2
DO2
E520.01/02/03/08
T
DO0
DH
T
LCR
DI1
DO1
QM-No.: 25DS0054E.02
T
LSO
DO0
DI0
T
LL
T
N
OUT11
OUT10
OUT1
OUT0
⋮
11
down