DS1236AN Maxim Integrated, DS1236AN Datasheet - Page 6

• Manufacturer Part Number: DS1236AN
• Description: Current & Power Monitors & Regulators
• Manufacturer: Maxim Integrated

Specifications of DS1236AN

• Product: Power Monitors
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 4.5 V
• Input Voltage Range: 4.5 V to 5.5 V

If the IN pin is connected to V
mode (RC=0). In the CMOS mode (RC=V
produce a pulse on the
to V
V
determined by the RC pin (see “Reset Control” section).
MEMORY BACKUP
The DS1236A provides all of the necessary functions required to battery back a static RAM. First, a
switch is provided to direct SRAM power from the incoming 5-volt supply (V
battery (V
CMOS microprocessor. For more information about nonvolatile processor applications, review the “Reset
Control” and “Wake Control” sections. Second, the same power-fail detection described in the power
monitor section is used to hold the chip enable output (
volts of V
low at the time power-fail detection occurs,
the period t
the corruption of data. If
unconditionally disabled within t
maximum propagation delay of 20 ns. NO TAG shows a typical nonvolatile SRAM application. The
DS1236A unlike the DS1236 can be operated without a battery. In this method of operation the V
1, must be grounded. In general, it would also be expected to have the RC, pin 8, grounded (NMOS
mode) since no battery backup is available.
FRESHNESS SEAL
In order to conserve battery capacity during initial construction of an end system, the DS1236A provides
a freshness seal that electrically disconnects the battery. This means that upon battery attach, the V
output will remain inactive until V
the battery is first attached, and V
cannot be invoked again without subsequent removal and reattachment of the battery.
POWER SWITCHING
When larger operating currents are required in a battery backed system, the 5-volt supply and battery
supply switches internal to the DS1236A may not be large enough to support the required load through
V
external power switching devices. As shown in Figure 8, power to the load is switched from V
battery on power-down, and from battery to V
output to switch between V
currently available discrete components. The transition threshold for PF and
battery voltage V
the external switch will be supplied by the battery. Therefore, if a discrete switch is used, this load should
be taken into consideration when sizing the battery.
RESET CONTROL
As mentioned above, the DS1236A supports two modes of operation. The CMOS mode is used when the
system incorporates a CMOS microprocessor which is battery backed. The NMOS mode is used when a
non-battery backed processor is incorporated. The mode is selected by the RC (Reset Control) pin. The
level of this pin distinguishes timing and level control on RST,
processor operation versus nonvolatile battery backup or battery-operated processor applications.
BAT
CCO
CCTP
. Once V
with a reasonable voltage drop. For these applications, the PF and
, the
BAT
BAT
CE
. This write protection mechanism occurs as V
), whichever is greater. This switched supply (V
expires. This delay of write protection until the current memory cycle is completed prevents
NMI
CC
BAT
decays to V
pin will remain high. The
, allowing a smooth transition between sources. The load applied to the PF pin from
NMI
CEO
BAT
pin. Given that any
BAT
CCO
is in an inactive state at the time of V
and V
, the
CC
CF
, the
CC
. During nominal supply conditions
is not present. Once V
is applied. This prevents V
CC
NMI
NMI
CCO
It provides better leakage and switchover performance than
CEO
output will pulse low as V
pin will either remain at V
) the power-down of V
CC
NMI
6 of 20
NMI
is held in its present state until
on power-up. The DS1336 is designed to use the
voltage will follow V
pulse has been completed by the time V
CEO
CC
) to within 0.3 volts of V
CC
is applied, the freshness seal is broken and
CCO
falls below V
CCO
) can also be used to battery back a
RST
CC
from powering other devices when
CC
out of tolerance at V
, and
PF
CC
OHL
decays to V
CEO
CC
-fail detection,
outputs are provided to gate
CCTP
down until V
or enter tri-state mode as
NMI
PF
will follow
CC
CEI
as specified. If
) or from an external
is set to the external
outputs for volatile
CC
is returned high or
CCTP
or to within 0.7
in the NMOS
CEO
CC
CCTP
CEI
CC
decays to
DS1236A
will not
BAT
will be
decays
with a
CEI
CC
, pin
CCO
PF
to
is