DS1236AN Maxim Integrated, DS1236AN Datasheet - Page 4

• Manufacturer Part Number: DS1236AN
• Description: Current & Power Monitors & Regulators
• Manufacturer: Maxim Integrated

Specifications of DS1236AN

• Product: Power Monitors
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 4.5 V
• Input Voltage Range: 4.5 V to 5.5 V

NON-MASKABLE INTERRUPT
The DS1236A generates a non-maskable interrupt
microprocessor. A precision comparator monitors the voltage level at the IN pin relative to a reference
generated by the internal band gap. The IN pin is a high-impedance input allowing for a user-defined
sense point. An external resistor voltage divider network (NO TAG) is used to interface with high voltage
signals. This sense point may be derived from the regulated 5-volt supply or from a higher DC voltage
level closer to the main system power input. Since the IN trip point V
for R1 and R2 can be determined by the equation as shown in NO TAG. Proper operation of the
DS1236A requires that the voltage at the IN pin be limited to V
voltage at the supply being monitored (V
approach to solving this equation is to select a value for R2 high enough to keep power consumption low,
and solve for R1. The flexibility of the IN input pin allows for detection of power loss at the earliest point
in a power supply system, maximizing the amount of time for microprocessor shutdown between
and RST or
When the supply being monitored decays to the voltage sense point, the DS1236A pulses the
to the active state for a minimum of 200 μs. The
domain hysteresis. That is, the monitored supply is sampled periodically at a rate determined by an
internal ring oscillator running at approximately 30 kHz (33 μs/cycle). Three consecutive samplings of
out-of-tolerance supply (below V
must be below the voltage sense point for approximately 100 μs or the comparator will reset. In this way,
power supply noise is removed from the monitoring function, preventing false trips. During a power-up,
any detected IN pin levels be low V
V
Removal of an active low level on the
less than V
signal during power-up results in an
on the relative voltage relationship between V
is tied to ground during power-up, the internal timeout will result in a pulse of 200 μs minimum to 500 μs
maximum. In contrast, if the IN pin is tied to V
power-up. Note that a fast-slewing power supply may cause the
power-up. This is of no consequence, however, since an RST will be active.
CC
rises to V
TP
RST
) or by the subsequent rise of the IN pin above V
CCTP
.
. As a result, any potential
SENSE
TP
NMI
) must occur at the IN pin to activate
NMI
by the comparator are disabled from reaching the
pulse of from 0 μs minimum to 500 μs maximum, depending
MAX
pin is controlled by either an internal timeout (when IN pin is
NMI
CC
) can also be derived as shown in NO TAG. A simple
and the IN pin voltage. As an example, when the IN pin
CCO
4 of 20
NMI
pulse will not be initiated until V
during power-up,
power-fail detection circuitry also has built-in time
NMI
for early warning of power failure to a
TP
. The initiation and removal of the
IN
. Therefore, the maximum allowable
NMI
TP
NMI
is 2.54 volts, the proper values
to be virtually nonexistent on
NMI
will not produce a pulse on
. Therefore, the supply
CC
reaches V
NMI
NMI
CCTP
pin until
DS1236A
output
.
NMI
NMI