DS1236-10 Maxim Integrated Products, DS1236-10 Datasheet
DS1236-10
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DS1236-10 Summary of contents
Page 1
... When an out-of-tolerance condition occurs, the microprocessor reset and power-fail outputs are forced active, and static RAM control unconditionally write protects external memory. The DS1236 also provides early warning detection of a user-defined threshold by driving a non-maskable interrupt. External reset control is provided by a pushbutton reset ...
Page 2
... Reset control and wake-up/sleep control inputs also provide the necessary signals for orderly shutdown and startup in battery backup and battery operated applications. A block diagram of the DS1236 is shown in Figure 1. PIN DESCRIPTION ...
Page 3
... Independent of the state of the RC pin, the watchdog is also disabled as soon falls CCTP PUSHBUTTON RESET An input pin is provided on the DS1236 for direct connection to a pushbutton. The pushbutton reset input requires an active low signal. Internally, this input is pulled high by a 10k resistor whenever V greater than V . The PBRST BAT driven to the active state for 25 ms minimum ...
Page 4
... This sense point may be derived from the regulated 5-volt supply or from a higher DC voltage level closer to the main system power input. Since the IN trip point V for R1 and R2 can be determined by the equation as shown in Figure 6. Proper operation of the DS1236 requires that the voltage at the IN pin be limited to V supply being monitored (V ) can also be derived as shown in Figure 6 ...
Page 5
... BAT CC BAT determined by the RC pin (see “Reset Control” section). MEMORY BACKUP The DS1236 provides all of the necessary functions required to battery back a static RAM. First, a switch is provided to direct SRAM power from the incoming 5-volt supply ( whichever is greater. This switched supply (V BAT microprocessor. For more information about nonvolatile processor applications, review the “ ...
Page 6
... RESET CONTROL As mentioned above, the DS1236 supports two modes of operation. The CMOS mode is used when the system incorporates a CMOS microprocessor which is battery backed. The NMOS mode is used when a non-battery backed processor is incorporated. The mode is selected by the RC (Reset Control) pin. The level of this pin distinguishes timing and level control on RST, processor operation versus nonvolatile battery backup or battery operated processor applications ...
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... NMI/FROM ST/INPUT Figure 3 POWER MONITOR, WATCHDOG Figure 4 PUSH BUTTON RESET TIMING Figure 5 NON-MASKABLE INTERRUPT Figure DS1236 ...
Page 8
... EXAMPLE 1: 5 VOLT SUPPLY 10k OHM, V ∴ 4.80 = EXAMPLE 2: 12 VOLT SUPPLY 10k OHM, V ∴ 9.00 = NONVOLATILE SRAM Figure 10k X 2.54 10k R1 + 10k X 2.54 10k 9. 5.00 = 17.7 VOLTS MAX 2. 4.80 VOLTS SENSE R1 = 8.9k OHM = 9.00 VOLTS SENSE R1 = 25.4k OHM DS1236 ...
Page 9
... When the RC pin is tied to ground, the DS1236 is designed to interface with NMOS processors which do not have the microamp currents required during a battery backed mode. Grounding the RC pin does, however, continue to support nonvolatile backup of system SRAM memory. Nonvolatile systems incorporating NMOS processors generally require that only the SRAM memory and/or timekeeping functions be battery backed ...
Page 10
... PBRST then be restarted as the watchdog times out and drives RST and started up by forcing the WC/ SC sleep mode by the processor and system power is lost, the DS1236 will wake up the next time V above V . These possibilities are illustrated in Figure 15. BAT When the sleep mode is invoked during normal power-valid conditions, all operation on the DS1236 is ...
Page 11
... RC pin is tied high (CMOS mode). Subsequent power-up of the V TP with the RC pin tied high will activate the RST and high-to-low transition on the WC/ invoke a Sleep mode for the DS1236. FRESHNESS SEAL Figure 8 NOTE: This series of pulses must be applied during normal +5 volt operation. POWER SWITCHING Figure 9 ...
Page 12
... CMOS MODE POWER-DOWN ( Figure 10 CCO DS1236 ...
Page 13
... NMOS MODE POWER-DOWN (RC = GND) Figure DS1236 ...
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... NMOS MODE POWER-UP (RC = GND) Figure DS1236 ...
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... CMOS MODE POWER-UP ( Figure 13 CCO DS1236 ...
Page 16
... WAKE/SLEEP CONTROL Figure 14 OPTIONS FOR INVOKING WAKEUP Figure DS1236 ...
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... MIN TYP BAT I CC01 I CC02 V V -0.3 CCO -0.7 CCO BAT -0.5V V -0. -0.7 OHL BAT R 10k PBRST DS1236 + 0. 0.5V CC (0°C to 70°C) MAX UNITS NOTES 4.5V to 5.5V) CC MAX UNITS NOTES μA 20 μA 0.1 2 100 ...
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... FPU t 25 100 RPU t 10 FB1 t 100 FB2 t .1 REC 100 400 PPF t STN t NRT t ARST t 30 100 BRST DS1236 MAX UNITS NOTES - μA +1.0 2 4.5V to 5.5V) CC MAX UNITS NOTES μs 175 μs 175 150 ms μs 500 μ μs ...
Page 19
... CEO CCO the maximum average load which the DS1236 can supply at V CCO1 during normal 5-volt operation the maximum average load which the DS1236 can supply through the V CCO2 retention battery supply operation, with a maximum drop of 0.8 volts μs. 5. With approximately V ...