DS1236AN Maxim Integrated, DS1236AN Datasheet - Page 11

• Manufacturer Part Number: DS1236AN
• Description: Current & Power Monitors & Regulators
• Manufacturer: Maxim Integrated

Specifications of DS1236AN

• Product: Power Monitors
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 4.5 V
• Input Voltage Range: 4.5 V to 5.5 V

the
additional
the supply voltage, as monitored by the IN pin, is above or below a selected operating value. This is
illustrated in NO TAG. As discussed above, the RC pin determines the timing relationships and levels of
several signals. The following section describes the power-up and power-down timing diagrams in more
detail.
TIMING DIAGRAMS
This section provides a description of the timing diagrams shown in Figure 9, Figure 10, Figure 11, and
Figure 12. These diagrams show the relative timing and levels in both the NMOS and the CMOS mode
for power-up and down. Figure 9 illustrates the relationship for power-down in CMOS mode. As V
falls, the IN pin voltage drops below V
failure via an active
V
to write protect the RAM. When the V
Figure 10 illustrates operation of the power-down sequence in NMOS mode. Once again, as power falls,
an
reaches V
and
loss of battery power.
Figure 11 shows the power-up sequence for the NMOS mode. As V
pins are deactivated. An active reset occurs as well as an
slew rates, reset will be maintained for the standard t
below V
The second
Figure 12 illustrates the power-up timing for CMOS mode. The principal difference is that the DS1236A
issues a reset immediately in the NMOS mode. In CMOS mode, a reset is issued when IN rises above
V
WAKE CONTROL/SLEEP CONTROL
The Wake/Sleep Control input (WC/
before entering the Stop mode. This feature allows the DS1236A, processor, and static RAM to maintain
nonvolatility in the lowest power mode possible. The processor may invoke the sleep mode in battery-
operated applications to conserve battery capacity when an absence of activity is detected. The operation
of this signal is shown in Figure 13. The DS1236A may subsequently be restarted by a high-to-low
transition on the
then be restarted as the watchdog times out and drives RST and
started up by forcing the WC/
sleep mode by the processor and system power is lost, the DS1236A will wake up the next time V
above V
When the sleep mode is invoked during normal power-valid conditions, all operation on the DS1236A is
disabled, thus leaving the
However, a loss of power during a sleep mode will result in an active RST and
RST
CCTP
TP
NMI
. Depending on the processor type, the
NMI
PF
voltage will follow V
, the power monitor trip point. Since the DS1236A is in CMOS mode, no reset is generated. The
will operate in a similar manner to CMOS mode. Notice that the
BAT
TP
is issued. This gives the processor time to save critical data in nonvolatile SRAM. When V
output. In addition, as long as the IN pin is less than V
CCTP
, a new
NMI
. These possibilities are illustrated in Figure 14.
NMI
, an active RST and
pulses. In this way, the
PBRST
and RST are provided to illustrate these possibilities.
NMI
NMI
will occur. If the processor does not issue a
input through human interface via a keyboard, touchpad, etc. The processor will
, which allows it to enter a sleep mode. As the power falls further, V
CC
NMI
down, but will fall no further than V
SC
, RST, and
pin high from an external source. Also, if the DS1236A is placed in a
RST
SC
CC
) allows the processor to disable all comparators on the DS1236A
are given. The RST voltage will follow V
ST
TP
reaches V
. As a result, the processor is notified of an impending power
NMI
pin can be used to allow the CMOS processor to determine if
RST
may terminate the Stop mode in the processor.
11 of 20
BAT
outputs disabled as well as the
RST
, a power-fail is issued via the PF and
timeout period. At a later time, if the IN pin falls
NMI
TP
. Although the
RST
, stimulation of the ST pin will result in
BAT
ST
CC
. At this time,
active. The DS1236A can also be
, a watchdog reset will also occur.
slews above V
NMI
NMI
will tri-state to prevent a
RST
CC
CEO
may be short due to
as it falls.
when the RC pin is
BAT
ST
, the PF and
is brought high
and IN inputs.
PF
CC
pins.
CEO
DS1236A
CC
crosses
, PF,
rises
PF
CC
CC