89H32T8G2ZCBLG IDT, 89H32T8G2ZCBLG Datasheet - Page 8

• Manufacturer Part Number: 89H32T8G2ZCBLG
• Description: Peripheral Drivers & Components - PCIs
• Manufacturer: IDT

Specifications of 89H32T8G2ZCBLG

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes
• Part # Aliases: IDT89H32T8G2ZCBLG

IDT 89HPES32T8G2 Data Sheet
JTAG_TRST_N
SWMODE[3:0]
JTAG_TCK
JTAG_TDO
JTAG_TMS
JTAG_TDI
RSTHALT
Signal
PERSTN
Signal
Type
Type
O
I
I
I
I
I
I
I
Global Reset. Assertion of this signal resets all logic inside PES32T8G2.
Reset Halt. When this signal is asserted during a PCI Express fundamental
reset, PES32T8G2 executes the reset procedure and remains in a reset
state with the Master and Slave SMBuses active. This allows software to
read and write registers internal to the device before normal device opera-
tion begins. The device exits the reset state when the RSTHALT bit is
cleared in the SWCTL register by an SMBus master.
Switch Mode. These configuration pins determine the PES32T8G2 switch
operating mode. Note: These pins should be static and not change follow-
ing the negation of PERSTN.
0x0 - Normal switch mode
0x1 - Normal switch mode with Serial EEPROM initialization
0x2 through 0x7 - Reserved
0x8 - Single partition with port 0 selected as the upstream port (port 2 dis-
0x9 - Single partition with port 2 selected as the upstream port (port 0 dis-
0xA - Single partition with Serial EEPROM initialization and port 0 selected
0xB - Single partition with Serial EEPROM initialization and port 2 selected
0xE - Reserved
0xF - Reserved
JTAG Clock. This is an input test clock used to clock the shifting of data
into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is
independent of the system clock with a nominal 50% duty cycle.
JTAG Data Input. This is the serial data input to the boundary scan logic or
JTAG Controller.
JTAG Data Output. This is the serial data shifted out from the boundary
scan logic or JTAG Controller. When no data is being shifted out, this signal
is tri-stated.
JTAG Mode. The value on this signal controls the test mode select of the
boundary scan logic or JTAG Controller.
JTAG Reset. This active low signal asynchronously resets the boundary
scan logic and JTAG TAP Controller. An external pull-up on the board is
recommended to meet the JTAG specification in cases where the tester
can access this signal. However, for systems running in functional mode,
one of the following should occur:
Table 5 System Pins (Part 2 of 2)
1) actively drive this signal low with control logic
2) statically drive this signal low with an external pull-down on the board
abled)
abled)
as the upstream port (port 2 disabled)
as the upstream port (port 0 disabled)
Table 6 Test Pins
8 of 39
Name/Description
Name/Description
November 28, 2011