89H32T8G2ZCBLG IDT, 89H32T8G2ZCBLG Datasheet - Page 3

• Manufacturer Part Number: 89H32T8G2ZCBLG
• Description: Peripheral Drivers & Components - PCIs
• Manufacturer: IDT

Specifications of 89H32T8G2ZCBLG

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes
• Part # Aliases: IDT89H32T8G2ZCBLG

Block Diagram
SMBus Interface
allowing every configuration register in the device to be read or written by an external agent. The master interface allows the default configuration
register values of the PES32T8G2 to be overridden following a reset with values programmed in an external serial EEPROM. The master interface is
also used by an external Hot-Plug I/O expander.
SSMBADDR2 pins. As shown in Figure 2, the master and slave SMBuses may only be used in a split configuration.
SMBus lines that connect to the serial EEPROM and I/O expander slaves. In the split configuration, the master and slave SMBuses operate as two
independent buses; thus, multi-master arbitration is not required.
IDT 89HPES32T8G2 Data Sheet
I
The PES32T8G2 contains two SMBus interfaces. The slave interface provides full access to the configuration registers in the PES32T8G2,
Each of the two SMBus interfaces contain an SMBus clock pin and an SMBus data pin. In addition, the slave SMBus has SSMBADDR1 and
The switch’s SMBus master interface does not support SMBus arbitration. As a result, the switch’s SMBus master must be the only master in the
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Multiplexer / Demultiplexer
Transaction Layer
Data Link Layer
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(Port 0)
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Frame Buffer
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8-Port Switch Core / 32 Gen2 PCI Express Lanes
Multiplexer / Demultiplexer
Transaction Layer
Data Link Layer
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Figure 2 Split SMBus Interface Configuration
(Port 1)
Route Table
Switch
Figure 1 Internal Block Diagram
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MSMBCLK
MSMBDAT
SSMBCLK
SSMBDAT
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EEPROM
Processor
Serial
SMBus
Master
...
Arbitration
Expander
Hot-Plug
Port
I/O
Devices
SMBus
Other
Scheduler
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Multiplexer / Demultiplexer
Transaction Layer
Data Link Layer
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November 28, 2011
(Port 7)
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