89H16NT16G2ZBHLG IDT, 89H16NT16G2ZBHLG Datasheet - Page 9

• Manufacturer Part Number: 89H16NT16G2ZBHLG
• Description: Peripheral Drivers & Components - PCIs
• Manufacturer: IDT

Specifications of 89H16NT16G2ZBHLG

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes
• Part # Aliases: IDT89H16NT16G2ZBHLG

CLKMODE[1:0]
JTAG_TRST_N
SWMODE[3:0]
GCLKFSEL
JTAG_TDO
JTAG_TMS
JTAG_TCK
JTAG_TDI
RSTHALT
Signal
PERSTN
Signal
Type
Type
O
I
I
I
I
I
I
I
I
I
Clock Mode. These signals determine the port clocking mode used by ports of the
device.
Global Clock Frequency Select. These signals select the frequency of the GCLKP
and GCLKN signals.
0x0 100 MHz
0x1 125 MHz
Fundamental Reset. Assertion of this signal resets all logic inside the device.
Reset Halt. When this signal is asserted during a switch fundamental reset sequence,
the switch remains in a quasi-reset state with the Master and Slave SMBuses active.
This allows software to read and write registers internal to the device before normal
device operation begins. The device exits the quasi-reset state when the RSTHALT bit
is cleared in the SWCTL register by an SMBus master.
Switch Mode. These configuration pins determine the switch operating mode.
0x0 - Single partition
0x1 - Single partition with Serial EEPROM initialization
0x2 - Single partition with Serial EEPROM Jump 0 initialization
0x3 - Single partition with Serial EEPROM Jump 1 initialization
0x4 through 0x7 - Reserved
0x8 - Single partition with reduced latency
0x9 - Single partition with Serial EEPROM initialization and reduced latency
0xA - Multi-partition with Unattached ports
0xB - Multi-partition with Unattached ports and I
0xC - Multi-partition with Unattached ports and Serial EEPROM initialization
0xD - Multi-partition with Unattached ports with I
0xE - Multi-partition with Disabled ports
0xF - Multi-partition with Disabled ports and Serial EEPROM initialization
JTAG Clock. This is an input test clock used to clock the shifting of data into or out of
the boundary scan logic or JTAG Controller. JTAG_TCK is independent of the system
clock with a nominal 50% duty cycle.
JTAG Data Input. This is the serial data input to the boundary scan logic or JTAG
Controller.
JTAG Data Output. This is the serial data shifted out from the boundary scan logic or
JTAG Controller. When no data is being shifted out, this signal is tri-stated.
JTAG Mode. The value on this signal controls the test mode select of the boundary
scan logic or JTAG Controller.
JTAG Reset. This active low signal asynchronously resets the boundary scan logic
and JTAG TAP Controller. An external pull-up on the board is recommended to meet
the JTAG specification in cases where the tester can access this signal. However, for
systems running in functional mode, one of the following should occur:
1) actively drive this signal low with control logic
2) statically drive this signal low with an external pull-down on the board
These pins should be static and not change following the negation of PERSTN.
ization
Table 7 System Pins
Table 8 Test Pins
9 of 33
Name/Description
Name/Description
2
2
C Reset
C Reset and Serial EEPROM initial-
April 16, 2013