89H16NT16G2ZBHLG IDT, 89H16NT16G2ZBHLG Datasheet - Page 6

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89H16NT16G2ZBHLG

Manufacturer Part Number
89H16NT16G2ZBHLG
Description
Peripheral Drivers & Components - PCIs
Manufacturer
IDT
Datasheet

Specifications of 89H16NT16G2ZBHLG

Product Category
Peripheral Drivers & Components - PCIs
Rohs
yes
Part # Aliases
IDT89H16NT16G2ZBHLG

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
89H16NT16G2ZBHLG
Manufacturer:
IDT
Quantity:
20 000
PE15RN[0]
PE16RN[0]
PE17RN[0]
PE18RN[0]
PE19RN[0]
PE14TN[0]
PE14TP[0]
PE15RP[0]
PE15TN[0]
PE15TP[0]
PE16RP[0]
PE16TN[0]
PE16TP[0]
PE17RP[0]
PE17TN[0]
PE17TP[0]
PE18RP[0]
PE18TN[0]
PE18TP[0]
PE19RP[0]
PE19TN[0]
PE19TP[0]
Signal
GCLKN[1:0]
GCLKP[1:0]
P08CLKN
P08CLKP
P16CLKN
P16CLKP
Signal
Type
O
O
O
O
O
O
Type
I
I
I
I
I
I
I
I
Table 2 PCI Express Interface Pins (Part 2 of 2)
PCI Express Port 14 Serial Data Transmit. Differential PCI Express transmit pair for
port 14.
PCI Express Port 15 Serial Data Receive. Differential PCI Express receive pair for
port 15.
PCI Express Port 15 Serial Data Transmit. Differential PCI Express transmit pair for
port 15.
PCI Express Port 16 Serial Data Receive. Differential PCI Express receive pair for
port 16.
PCI Express Port 16 Serial Data Transmit. Differential PCI Express transmit pair for
port 16.
PCI Express Port 17 Serial Data Receive. Differential PCI Express receive pair for
port 17.
PCI Express Port 17 Serial Data Transmit. Differential PCI Express transmit pair for
port 17.
PCI Express Port 18 Serial Data Receive. Differential PCI Express receive pair for
port 18.
PCI Express Port 18 Serial Data Transmit. Differential PCI Express transmit pair for
port 18.
PCI Express Port 19 Serial Data Receive. Differential PCI Express receive pair for
port 19.
PCI Express Port 19 Serial Data Transmit. Differential PCI Express transmit pair for
port 19.
Global Reference Clock. Differential reference clock input pairs. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic. The frequency of the differential reference
clock is determined by the GCLKFSEL signal.
Note: Both pairs of the Global Reference Clocks must be connected to and
derived from the same clock source. Refer to the Overview section of
Chapter 2 in the PES16NT16G2 User Manual for additional details.
Port Reference Clock. Differential reference clock pair associated with
port 8.
Port Reference Clock. Differential reference clock pair associated with
port 16.
Table 3 Reference Clock Pins
6 of 33
Name/Description
Name/Description
April 16, 2013

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